公开(公告)号：US20080290510A1

公开(公告)日：2008-11-27

申请号：US11752449

申请日：2007-05-23

Applicant: Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

Inventor： Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

IPC: H01L23/485

CPC classification number: H05K1/116 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K2201/09454 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.

Abstract translation: 提供具有集成电路的微电子封装。 微电子封装包括多个电介质层压层，铜电路在介电层压层之间，其中铜电路包括电路迹线，以及球栅阵列/焊盘电极阵列，可操作地连接到铜电路，从而导通发生。 此外，靠近铜电路和球栅阵列/接地栅阵列的连接，保护铜舌低于电路迹线的延伸线，使得保护铜舌防止电路迹线受到在 电介质层压层或球栅阵列/焊盘阵列。

公开(公告)号：US20080290474A1

公开(公告)日：2008-11-27

申请号：US11751786

申请日：2007-05-22

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L23/52 ,  G06F17/50 ,  H01L21/3205

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 具有改进的传输线完整性和增加的布线密度的多层电路基板和方法使用选择性地施加的传输线参考平面金属层来实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输之间的电容引起的阻抗下降 线参考平面金属层。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US07376914B2

公开(公告)日：2008-05-20

申请号：US11379446

申请日：2006-04-20

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

Abstract: A method for designing a power distribution system including: receiving a cross section file that contains the layout of a PCB including a location of one or more power sinks and sources on the PCB; creating an initial power distribution system; evaluating the initial power distribution system against a cost function; creating a new power distribution system; evaluating the new power distribution system against the cost function; determining if the cost function associated with the new power distribution system is equal to or greater than a stop criterion; and creating another new power distribution system if the cost function associated with the new power distribution system is greater than the stop criterion.

Abstract translation: 一种用于设计配电系统的方法，包括：接收包含PCB的布局的横截面文件，所述布局包括PCB上的一个或多个电源和源的位置; 创建初始配电系统; 根据成本函数评估初始配电系统; 建立新的配电系统; 根据成本函数评估新的配电系统; 确定与新配电系统相关联的成本函数是否等于或大于停止准则; 并且如果与新配电系统相关联的成本函数大于停止标准，则创建另一新的配电系统。

公开(公告)号：US20070288182A1

公开(公告)日：2007-12-13

申请号：US11420825

申请日：2006-05-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F19/00 ,  G06F11/30 ,  H02H7/00

CPC classification number: G06F1/305

Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。 将经过时间平均的第一电压与第二电压进行比较。 生成信号以指示处理器内的电路以启动动作以使电压进一步下降。