利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

133 条记录 (耗时 0.034 秒)

    Output regulator system and method
    71.
    发明授权
    Output regulator system and method 有权
    输出调节器系统及方法

    公开(公告)号：US07023192B2

    公开(公告)日：2006-04-04

    申请号：US10712290

    申请日：2003-11-12

    申请人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

    发明人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

    IPC分类号： G05F1/40

    CPC分类号： H02M3/157 ,  H02M1/088 ,  H02M1/38 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/0025 ,  H02M2001/0048 ,  H03K5/1565 ,  H03K17/122 ,  H03K17/167 ,  H03K17/6871 ,  Y02B70/1466 ,  Y02B70/1491

    摘要： An output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage. An output filter to filter the power output to generate the regulated output. An output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the power stage.

    摘要翻译： 输出调节器，用于将输入电压转换为稳压输出。 输出调节器包括从输入电压产生功率输出的功率级。 输出滤波器，用于过滤功率输出以产生调节输出。 一种输出传感器，用于产生数字感测信号，以指示包括至少三个参考范围内的调节输出。 所述至少三个参考范围中的每一个包括调节输出的多个可能值。 响应于数字感测信号的数字控制器产生驱动信号以控制功率级。

    Cable tester with insertion loss estimator
    72.
    发明授权
    Cable tester with insertion loss estimator 有权
    带插入损耗估计器的电缆测试仪

    公开(公告)号：US06995551B1

    公开(公告)日：2006-02-07

    申请号：US11066739

    申请日：2005-02-25

    申请人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    发明人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    IPC分类号： G01R31/11

    CPC分类号： G01R31/083 ,  G01R31/088 ,  G01R31/11

    摘要： A physical layer device including a first port, a second port, and a cable that has one end that communicates with the first port and an opposite end that communicates with the second port. A cable tester tests the cable to determine a cable status, which includes an open status, a short status, and a normal status. A pretest module senses activity on the cable and selectively enables testing depending upon the sensed activity. A test module transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.

    摘要翻译： 一种包括第一端口，第二端口和具有与第一端口通信的一端的电缆以及与第二端口通信的相对端的物理层设备。 电缆测试仪测试电缆以确定电缆状态，包括打开状态，短状态和正常状态。 预测试模块感测电缆上的活动，并根据感测到的活动选择性地启用测试。 测试模块在电缆上传输测试脉冲，测量反射幅度，计算电缆长度，并根据测量的幅度和计算的电缆长度确定电缆状态。 频率合成器与电缆通信，并且选择性地以第一端口上的多个频率输出多个信号。 插入损耗计算器接收第二端口上的信号并估计插入损耗。

    Cable tester
    74.
    发明授权
    Cable tester 有权
    电缆测试仪

    公开(公告)号：US06982557B1

    公开(公告)日：2006-01-03

    申请号：US10979302

    申请日：2004-11-02

    申请人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    发明人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    IPC分类号： G01R31/02

    CPC分类号： G01R31/083 ,  G01R31/088 ,  G01R31/11

    摘要： A physical layer device according to some implementations includes a cable tester that generates a test pulse on a cable and that determines a cable status including an open status, a short status, and a normal status. A cable impedance estimator communicates with the cable tester and estimates an impedance of the cable based on a reflection amplitude of the test pulse.

    摘要翻译： 根据一些实现的物理层设备包括电缆测试器，其在电缆上产生测试脉冲，并且确定包括打开状态，短状态和正常状态的电缆状态。 电缆阻抗估计器与电缆测试器通信，并基于测试脉冲的反射幅度来估计电缆的阻抗。

    Implementing reduced-state viterbi detectors
    78.
    发明授权
    Implementing reduced-state viterbi detectors 失效
    实现降态维特比探测器

    公开(公告)号：US06597742B1

    公开(公告)日：2003-07-22

    申请号：US09603703

    申请日：2000-06-27

    申请人： Runsheng He ,  Joao R. Cruz

    发明人： Runsheng He ,  Joao R. Cruz

    IPC分类号： H04L512

    CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L25/03229

    摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

    摘要翻译： 提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。 该方法使用补码状态分组技术，其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。 所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失，而复杂度降低了约两倍。

    Cable tester
    79.
    发明授权
    Cable tester 有权
    电缆测试仪

    公开(公告)号：US08829917B1

    公开(公告)日：2014-09-09

    申请号：US13470893

    申请日：2012-05-14

    申请人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    发明人： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

    IPC分类号： G01R31/11

    CPC分类号： H04L43/50 ,  G01R31/11 ,  H04L12/10

    摘要： A physical layer device configured to interface with a plurality of pairs of wires. The physical layer device includes a cable test module configured to transmit a pulse over the plurality of pairs of wires, measure a reflection of the pulse as received from the plurality of pairs of wires, and determine whether a short circuit exists in one of the plurality of pairs of wires based on the measure of the reflection of the pulse. An autonegotiation module is configured to perform autonegotiation to establish a link at a particular speed over the plurality of pairs of wires. The particular speed at which the link is established over the plurality of pairs of wires is based, at least in part, on whether a short circuit exists in one of the plurality of pairs of wires as determined by the cable test module.

    摘要翻译： 物理层设备，被配置为与多对线对接口。 物理层设备包括：电缆测试模块，被配置为在所述多对导线上传输脉冲，测量从所述多对导线接收的所述脉冲的反射，并且确定所述多个导线之一中是否存在短路 的基于脉冲反射测量的电线对。 自动协商模块被配置为执行自动协商以在多对线路上以特定速度建立链路。 至少部分地基于由电缆测试模块确定的多对线中的一条线路是否存在短路，在多对线路上建立链路的特定速度是基于的。

    Circuit and method for finding the sampling phase and canceling intersymbol interference in a decision feedback equalized receiver
    80.
    发明授权
    Circuit and method for finding the sampling phase and canceling intersymbol interference in a decision feedback equalized receiver 有权
    用于在判决反馈均衡接收机中找到采样相位和消除符号间干扰的电路和方法

    公开(公告)号：US08767813B1

    公开(公告)日：2014-07-01

    申请号：US11656729

    申请日：2007-01-23

    申请人： Runsheng He

    发明人： Runsheng He

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03057 ,  H04L7/0062 ,  H04L7/0334 ,  H04L25/0307 ,  H04L25/4917 ,  H04L2025/0349

    摘要： A circuit comprises an analog to digital converter (ADC) that samples a received signal based on a sampling clock. A feed forward filter communicates with the ADC and does not remove first precursor intersymbol interference from the received signal. An adaptive timing loop circuit that adjusts a timing phase of the sampling clock of said ADC to remove the first precursor intersymbol interference from the received signal. The adaptive timing loop circuit adjusts the timing phase based on at least one of an estimate signal and a loop gain control constant.

    摘要翻译： 电路包括基于采样时钟对接收信号进行采样的模数转换器（ADC）。 前馈滤波器与ADC通信，不会从接收到的信号中消除第一个前兆码间干扰。 一种自适应定时环路电路，其调整所述ADC的采样时钟的定时相位，以从接收的信号中去除第一前兆符号间干扰。 自适应定时环路电路基于估计信号和环路增益控制常数中的至少一个来调整定时相位。