公开(公告)号：US20210264964A1

公开(公告)日：2021-08-26

申请号：US16798718

申请日：2020-02-24

Applicant: SanDisk Technologies LLC

Inventor： Sarath Puthenthermadam ,  Yu-Chung Lien ,  Huai-Yuan Tseng

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/14 ,  G11C5/02 ,  G11C5/14

Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

公开(公告)号：US20210241836A1

公开(公告)日：2021-08-05

申请号：US16778821

申请日：2020-01-31

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

公开(公告)号：US11037635B1

公开(公告)日：2021-06-15

申请号：US16784171

申请日：2020-02-06

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Tomer Eliash ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: Apparatuses and techniques are described for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.

公开(公告)号：US11017869B2

公开(公告)日：2021-05-25

申请号：US16893626

申请日：2020-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US10861537B1

公开(公告)日：2020-12-08

申请号：US16668886

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Abhijith Prakash

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/408

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

公开(公告)号：US10559370B2

公开(公告)日：2020-02-11

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10541038B2

公开(公告)日：2020-01-21

申请号：US16205165

申请日：2018-11-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xiang Yang ,  Zhenming Zhou ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

公开(公告)号：US20190392909A1

公开(公告)日：2019-12-26

申请号：US16014850

申请日：2018-06-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

公开(公告)号：US20190392893A1

公开(公告)日：2019-12-26

申请号：US16019456

申请日：2018-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Dengtao Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Zhongguang Xu ,  Yanli Zhang ,  Jin Liu

IPC: G11C11/56 ,  G11C16/24 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.

公开(公告)号：US10482984B2

公开(公告)日：2019-11-19

申请号：US15952752

申请日：2018-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.