公开(公告)号：US20240065004A1

公开(公告)日：2024-02-22

申请号：US18366723

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Seungyeon Kim ,  Daeseok Byeon

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/35 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/35 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.

公开(公告)号：US11862624B2

公开(公告)日：2024-01-02

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L23/538 ,  H01L27/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L27/0255 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/0629 ,  H10B41/27 ,  H10B43/27

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

公开(公告)号：US11837293B2

公开(公告)日：2023-12-05

申请号：US17898885

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/00 ,  G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20230255036A1

公开(公告)日：2023-08-10

申请号：US18085188

申请日：2022-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beakhyung CHO ,  Daeseok Byeon

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/40

Abstract: In some embodiments, a non-volatile memory device includes a first semiconductor layer that includes a first memory cell array disposed on a first cell region, a second memory cell array disposed on a second cell region, and a first metal pad. The non-volatile memory device further includes a second semiconductor layer that includes a first peripheral circuit disposed on a first region and coupled to the first memory cell array, a second peripheral circuit disposed on a second region and coupled to the second memory cell array, and a second metal pad. The first region includes a first peripheral circuit region that overlaps the first cell region in the vertical direction, and a second peripheral circuit region that does not overlap the first cell region in the vertical direction, and the second region overlaps the second cell region in the vertical direction.

公开(公告)号：US20230230941A1

公开(公告)日：2023-07-20

申请号：US18126996

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC: H01L23/60 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L23/60 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

公开(公告)号：US11621256B2

公开(公告)日：2023-04-04

申请号：US17393934

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US11411018B2

公开(公告)日：2022-08-09

申请号：US16923636

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11565

Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

公开(公告)号：US11348848B2

公开(公告)日：2022-05-31

申请号：US17006186

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11289150B2

公开(公告)日：2022-03-29

申请号：US17196183

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

IPC: G11C11/40 ,  G11C11/4072 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4099

Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

公开(公告)号：US11264084B2

公开(公告)日：2022-03-01

申请号：US16871815

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C11/4093 ,  G11C16/08 ,  G11C16/04 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/408

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.