公开(公告)号：US11217327B2

公开(公告)日：2022-01-04

申请号：US17039798

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Min Kang ,  Dongku Kang ,  Kwang Won Kim ,  HyunJin Kim

IPC: G06F13/20 ,  G06F13/38 ,  G06F3/06 ,  G11C29/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C5/02 ,  G06F11/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

公开(公告)号：US20210091105A1

公开(公告)日：2021-03-25

申请号：US16923636

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768

Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

公开(公告)号：US09165672B2

公开(公告)日：2015-10-20

申请号：US14077606

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang ,  Dae Yeal Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C17/06

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。

公开(公告)号：US11723208B2

公开(公告)日：2023-08-08

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C11/00 ,  H10B43/40 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11503748B2

公开(公告)日：2022-11-15

申请号：US17166248

申请日：2021-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haejin Lee ,  Dongku Kang ,  Jihong Kim ,  Min Park ,  Yunjeong Park ,  Kyuhwan Lee ,  Jinhwan Jung ,  Ahreum Hwang ,  Kyungha Koo

IPC: H05K9/00 ,  H05K7/20 ,  H05K1/02

Abstract: A portable communication device is provided. A portable communication device includes a first nanofiber member having a first density, a second nanofiber member attached to the first nanofiber member and having a second density lower than the first density, a heat transfer member positioned on or above the second nanofiber member, and a conductive material coated on at least a portion of the first nanofiber member and the second nanofiber member. At least some of the conductive material may penetrate into the first nanofiber member or the second nanofiber member. Various other embodiments may be possible.

公开(公告)号：US11430806B2

公开(公告)日：2022-08-30

申请号：US16878756

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

公开(公告)号：US11430804B2

公开(公告)日：2022-08-30

申请号：US16809059

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.

公开(公告)号：US09520201B2

公开(公告)日：2016-12-13

申请号：US14853488

申请日：2015-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang ,  Dae Yeal Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/06 ,  G11C17/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.

Abstract translation: 提供了一种非易失性存储器件，其包括页缓冲器单元。 页面缓冲器单元包括第一页缓冲器，其包括被配置为存储第一高位数据的第一A锁存器和被配置为存储第一低位数据的第一B锁存器，以及包括第二A锁存器的第二页缓冲器，其被配置为存储第二高位 数据和第二B锁存器，其被配置为存储第二低位数据。 设定的脉冲可以施加到第一A锁存器和第二B锁存器，或者施加到第二A锁存器和第一B锁存器两者。 非易失性存储器件可以提供高写入性能并且可以在手持终端的超时周期内进行响应。

公开(公告)号：US09396797B2

公开(公告)日：2016-07-19

申请号：US14151534

申请日：2014-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.

Abstract translation: 一种非易失性存储装置的编程方法包括将要存储在连接到第一字线的第一存储单元中的第一字线数据和要存储在连接到第二字线的第二存储单元中的第二字线数据进行加载; 根据第一字线数据设置高位线; 在高位线建立之后关闭位线共享晶体管; 根据第二字线数据设置低位线; 使用高位线对所述第一存储器单元执行第一编程操作; 打开位线共享晶体管; 以及使用所述下位线对所述第二存储器单元执行第二编程操作。 位线共享晶体管响应于位线共享信号而电连接高位线和低位线。

公开(公告)号：US08537612B2

公开(公告)日：2013-09-17

申请号：US13688249

申请日：2012-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621

Abstract: A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data.

Abstract translation: 一种对非易失性存储器件进行编程的方法包括：基于较低位数据选择性地将存储器单元从第一状态编程到第二状态，有选择地将存储器单元从第二状态编程到对应于较低位数据的中间状态，以及选择性编程 存储单元基于高位数据从中间状态到第三或第四状态。