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公开(公告)号:US20210118877A1
公开(公告)日:2021-04-22
申请号:US16991530
申请日:2020-08-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaemun Kim , Gyeom Kim , Dahye Kim , Jinbum Kim , Kyungin Choi , llgyou Shin , Seunghun Lee
IPC: H01L27/088 , H01L21/8234 , H01L21/02
Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.
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公开(公告)号:US10062754B2
公开(公告)日:2018-08-28
申请号:US14491117
申请日:2014-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinbum Kim , Bonyoung Koo , Seokhoon Kim , Chul Kim , Kwan Heum Lee , Byeongchan Lee , Sujin Jung
IPC: H01L29/78 , H01L29/08 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC classification number: H01L29/0847 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.
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公开(公告)号:US09698244B2
公开(公告)日:2017-07-04
申请号:US15062742
申请日:2016-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinbum Kim , Jaeyoung Park , Donghun Lee , Jeongho Yoo , Jieon Yoon , Kwan Heum Lee , Choeun Lee , Bonyoung Koo
IPC: H01L29/66 , H01L29/04 , H01L29/12 , H01L29/417 , H01L29/423 , H01L29/40 , H01L21/30
CPC classification number: H01L29/66636 , H01L21/3003 , H01L29/045 , H01L29/0847 , H01L29/12 , H01L29/165 , H01L29/401 , H01L29/41766 , H01L29/42356 , H01L29/66545 , H01L29/78
Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.
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