-
公开(公告)号：US08659165B2
公开(公告)日：2014-02-25
申请号：US12429375
申请日：2009-04-24
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L23/48
CPC分类号： H01L21/76885 , H01L21/76877 , H01L23/5226 , H01L23/5227 , H01L23/5286 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
摘要翻译： 一种包含垂直互连的集成电路，其包括连续围绕一个或多个介电柱的互连金属区域。 垂直互连电接触下导电结构的顶表面。 上导电结构接触垂直互连的顶表面。 形成集成电路的过程包括形成具有连续围绕一个或多个介电柱的互连金属区域的垂直互连。 垂直互连电接触下导电结构的顶表面，并且上导电结构接触垂直互连的顶表面。
-
72.发明授权Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer 有权增加铁电电容层的曝光工具对准信号强度公开(公告)号：US08586130B2
公开(公告)日：2013-11-19
申请号：US12889851
申请日：2010-09-24
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , Y10T29/42 , H01L2924/00
摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
摘要翻译： 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层，使得对准标记的形貌在反射层中复制，使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层，并且可以是金属的，电介质的或两者的。 反射层可以在整个IC上是全局的，或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层，可能来自添加的蚀刻停止层的辅助，或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。
-
公开(公告)号：US08466569B2
公开(公告)日：2013-06-18
申请号：US12411914
申请日：2009-03-26
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , Y10T29/42 , H01L2924/00
摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
-
公开(公告)号：US08268696B2
公开(公告)日：2012-09-18
申请号：US12964430
申请日：2010-12-09
IPC分类号： H01L21/762
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
-
公开(公告)号：US20120149189A1
公开(公告)日：2012-06-14
申请号：US13396420
申请日：2012-02-14
申请人： Gul B. Basim , Scott R. Summerfelt , Ted S. Moise
发明人： Gul B. Basim , Scott R. Summerfelt , Ted S. Moise
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/3003 , H01L21/0217 , H01L21/02274 , H01L21/76829 , H01L21/76832 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
摘要翻译： 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。
-
公开(公告)号：US20110306176A1
公开(公告)日：2011-12-15
申请号：US12964430
申请日：2010-12-09
IPC分类号： H01L21/762
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻，接触金属沉积和选择性接触金属去除过程期间形成在内部的PMD柱阵列。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。
-
77.发明授权公开(公告)号：US07935543B2
公开(公告)日：2011-05-03
申请号：US12472265
申请日：2009-05-26
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.
摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。
-
公开(公告)号：US07894235B2
公开(公告)日：2011-02-22
申请号：US12856279
申请日：2010-08-13
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
摘要翻译： 包含电流镜感应放大器的F-RAM存储器件。 包含耦合到负电压发生器的电流镜检测放大器的F-RAM存储器件。 一种在包含电流镜像放大器的2T2C F-RAM器件中读取数据并将数据恢复回F-RAM单元的方法。 从1T1C F-RAM设备读取数据并将数据恢复回F-RAM单元的方法。
-
公开(公告)号：US20110019461A1
公开(公告)日：2011-01-27
申请号：US12507449
申请日：2009-07-22
CPC分类号： G11C11/22
摘要： A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.
摘要翻译： 一种操作包含可编程数据存储组件的集成电路的过程，该可编程数据存储组件包括至少一个数据铁电电容器和至少一个额外的铁电电容器，其中在每次读取操作之后从状态电路中去除功率。 一种操作包含可编程数据存储部件的集成电路的过程，该可编程数据存储部件包括至少一个数据铁电电容器和至少一个附加的铁电电容器，其中在每次写入操作之后从状态电路去除功率。 一种操作包含可编程数据存储部件的集成电路的处理，该可编程数据存储部件包括四个数据铁电电容器，其中在每次读取操作之后和每次写入操作之后，从状态电路中去除功率。
-
公开(公告)号：US20110004859A1
公开(公告)日：2011-01-06
申请号：US12883741
申请日：2010-09-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , H01L22/26 , H01L27/0207 , H01L27/11507 , Y02P90/265
摘要： A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
摘要翻译： 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。
-
-
-
-
-
-
-
-
-
搜索结果
184 条记录 (耗时 0.036 秒)
