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    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
    72.
    发明申请
    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion 有权
    方法和存储器系统具有双数据选通模式和单反数据选通模式之间的模式选择

    公开(公告)号：US20050005053A1

    公开(公告)日：2005-01-06

    申请号：US10733413

    申请日：2003-12-12

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401

    CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

    摘要： A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

    摘要翻译： 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

    Voltage and time control circuits
    73.
    发明授权
    Voltage and time control circuits 有权
    电压和时间控制电路

    公开(公告)号：US06788132B2

    公开(公告)日：2004-09-07

    申请号：US10147553

    申请日：2002-05-17

    申请人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    发明人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    IPC分类号： G05F302

    CPC分类号： G05F1/465

    摘要： Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

    摘要翻译： 提供了集成电路，其包括电压控制电路，其被配置为将预定电路电压规范之外的电路电压调整到预定电路电压规范内，使得集成电路器件不再有缺陷。 还提供了集成电路，其包括信号时间延迟控制电路，其被配置为将预定电路延迟时间规范之外的电路延迟时间调整到预定电路延迟时间规范内，使得集成电路装置不再有缺陷。 还提供了相应的操作方法。

    Semiconductor device, a parallel interface system and methods thereof
    75.
    发明授权
    Semiconductor device, a parallel interface system and methods thereof 有权
    半导体器件，并行接口系统及其方法

    公开(公告)号：US08780668B2

    公开(公告)日：2014-07-15

    申请号：US13483719

    申请日：2012-05-30

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

    摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

    摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

    Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell
    77.
    发明授权
    Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell 有权
    位线读出放大器，包括相同的存储器核心以及从存储器单元感测电荷的方法

    公开(公告)号：US08432762B2

    公开(公告)日：2013-04-30

    申请号：US13006832

    申请日：2011-01-14

    申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

    摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

    摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

    Semiconductor device, a parallel interface system and methods thereof
    80.
    发明申请
    Semiconductor device, a parallel interface system and methods thereof 有权
    半导体器件，并行接口系统及其方法

    公开(公告)号：US20110135030A1

    公开(公告)日：2011-06-09

    申请号：US12929627

    申请日：2011-02-04

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    IPC分类号： H04L27/00

    CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

    摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

    摘要翻译： 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。