公开(公告)号：US08039890B2

公开(公告)日：2011-10-18

申请号：US11743265

申请日：2007-05-02

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

IPC分类号： H01L29/792

CPC分类号： G06F7/588 ,  H03B29/00

摘要： A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x≧0, 1≧y≧0, z≧0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.

摘要翻译： 随机数发生装置包括：半导体器件，包括源区域，漏极区域，设置在源极区域和漏极区域之间的沟道区域;以及绝缘部分，设置在沟道区域上，绝缘部分包括捕获绝缘膜， 基于悬挂键并由六（SiO 2）y（Si 3 N 4）1-yMz表示的陷阱（M是除Si，O和N之外的元素，x≥0，1≥y≥0，z≥0， x = 0且y = 1，z = 0），根据陷阱中捕获的电荷量随机地变化的信道区域的电导率和连接到半导体器件的随机数生成单元，并基于 通道区域的电导率随机变化。

公开(公告)号：US20090302394A1

公开(公告)日：2009-12-10

申请号：US12237152

申请日：2008-09-24

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H01L27/06 ,  H01L21/8238

CPC分类号： H01L27/0688 ,  H01L27/101

摘要： A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

摘要翻译： 具有纳米线，碳纳米管，磁存储单元，相变存储单元，铁电存储单元等集成功能元件的互补金属氧化物半导体（CMOS）电路。 功能器件与CMOS电路集成。 功能器件通过例如直接接合，阳极结合或扩散接合来结合到CMOS电路的顶表面。 功能器件在载体晶片上制造和处理，并且在功能器件上沉积附着层（例如SiO 2）。 然后，连接CMOS电路和附着层。 移除载体晶片（例如通过蚀刻）。 功能器件通过附着层保持连接到CMOS电路。 孔径通过附着层蚀刻，以提供用于CMOS电路和功能器件之间的电连接的路径。

公开(公告)号：US07336525B2

公开(公告)日：2008-02-26

申请号：US11061951

申请日：2005-02-17

申请人： Shinobu Fujita ,  Thomas H. Lee

发明人： Shinobu Fujita ,  Thomas H. Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/005 ,  G11C5/02 ,  G11C14/0081

摘要： A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the at least one nonvolatile memory includes a high resistive state and a low resistive state. The volatile data storage circuit can include cross-coupled inverters, cross-coupled NAND gates, or another volatile data storage circuit. The nonvolatile memories can include a spin-injection magnetic tunnel junction memory, a magnetic tunnel junction memory, a metal insulator phase change memory, an organic memory, or some other memory with two resistive states.

摘要翻译： 在断电时保存存储的数据的存储电路包括易失性数据存储电路; 以及耦合在所述易失性数据存储电路内的至少一个非易失性存储器，其中所述至少一个非易失性存储器包括高电阻状态和低电阻状态。 易失性数据存储电路可以包括交叉耦合反相器，交叉耦合NAND门或另一易失性数据存储电路。 非易失性存储器可以包括自旋注入磁隧道结存储器，磁性隧道结存储器，金属绝缘体相变存储器，有机存储器或具有两个电阻状态的一些其它存储器。

公开(公告)号：US07068069B2

公开(公告)日：2006-06-27

申请号：US10943973

申请日：2004-09-20

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  G06F7/38 ,  G11C8/00

CPC分类号： H03K19/17748 ,  G11C16/02 ,  G11C16/10 ,  H03K3/45 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/1778

摘要： A control circuit for providing a control signal to build a logic circuit includes a latch circuit including first and second inverted logic gates; a first variable resistive memory provided between an output of the first inverted logic gate and an input of the second inverted logic gate, the first variable resistive memory configured to store a resistance value in accordance with a write signal; and a resistive element provided between an input of the first inverted logic gate, wherein the output of the second inverted logic gate serves to transmit the control signal.

摘要翻译： 用于提供用于构建逻辑电路的控制信号的控制电路包括包括第一和第二反相逻辑门的锁存电路; 第一可变电阻存储器，被设置在所述第一反相逻辑门的输出端和所述第二反相逻辑门极的输入端之间，所述第一可变电阻存储器被配置为根据写信号存储电阻值; 以及设置在第一反相逻辑门的输入之间的电阻元件，其中第二反相逻辑门的输出用于发送控制信号。

公开(公告)号：US06208000B1

公开(公告)日：2001-03-27

申请号：US09304343

申请日：1999-05-04

申请人： Tetsufumi Tanamoto ,  Shinobu Fujita ,  Koichiro Inomata

发明人： Tetsufumi Tanamoto ,  Shinobu Fujita ,  Koichiro Inomata

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  H01L29/42332 ,  H01L29/7888

摘要： A semiconductor device according to the invention is constructed as below. A charge accumulating layer which contains a magnetic substance is formed directly on a semiconductor substrate, and a gate insulating film is formed on the charge accumulating layer. Further, a gate electrode is formed on the gate insulating film, and source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween. Another semiconductor device according to the invention is constructed as below. A first gate insulating film formed on a semiconductor substrate, and a charge accumulating layer which contains a magnetic substance is formed on the first gate insulating film. Further, a second gate insulating film is formed on the charge accumulating layer, and a gate electrode is formed on the second gate insulating film. Source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween.

摘要翻译： 根据本发明的半导体器件如下构造。 在半导体基板上直接形成含有磁性物质的电荷蓄积层，在电荷蓄积层上形成栅极绝缘膜。 此外，在栅极绝缘膜上形成栅电极，形成在半导体基板的表面部分中的栅极电极和漏极区域，使得栅电极介于其间。 根据本发明的另一半导体器件如下构造。 形成在半导体衬底上的第一栅极绝缘膜和含有磁性物质的电荷累积层形成在第一栅极绝缘膜上。 此外，在电荷累积层上形成第二栅极绝缘膜，在第二栅极绝缘膜上形成栅电极。 源极和漏极区域形成在半导体衬底的表面部分中，使得栅电极介于其间。

公开(公告)号：US6157047A

公开(公告)日：2000-12-05

申请号：US143106

申请日：1998-08-28

申请人： Shinobu Fujita ,  Atsushi Kurobe

发明人： Shinobu Fujita ,  Atsushi Kurobe

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L27/15 ,  H01L29/66 ,  H01L33/04 ,  H01L33/16 ,  H01L33/34 ,  H01L33/44 ,  H01L29/00

CPC分类号： H01L33/34 ,  H01L33/18 ,  H01L27/15

摘要： A device structure provides improved efficiency of light emission from a light emitting element made of silicon while rendering such emission electrically controllable. Silicon in the light emitting element comprises fine microcrystals, which are miniaturized sufficiently to cause a quantum size effect. The microcrystals may be 10 nanometers (nm) or less in grain size. A dielectric film of 5 nm thick or less is formed containing therein such microcrystals. The microcrystal structure section is disposed between p- and n-type semiconductor layers. These layers are brought into electrical contact with the microcrystal structure only, while causing the remaining portions to be electrically insulative by a dielectric film or the like. Elementary particles of the opposite polarities, e.g. electrons and holes, are injected by tunnel effect into the microcrystals resulting in emission of light rays with increased efficiency.

摘要翻译： 器件结构提供了由硅制成的发光元件提供的发光效率，同时使这种发射电可控制。 发光元件中的硅包括细小的微晶，其小型化以产生量子尺寸效应。 微晶体的粒径可以为10纳米（nm）以下。 形成5nm以下的电介质膜，其中含有这样的微晶。 微晶结构部分设置在p型和n型半导体层之间。 这些层仅与微结晶结构电接触，同时通过介电膜等使剩余部分电绝缘。 具有相反极性的基本粒子，例如 电子和空穴通过隧道效应注入到微晶中，导致光线的发射效率提高。