公开(公告)号：US6080619A

公开(公告)日：2000-06-27

申请号：US85903

申请日：1998-05-27

申请人： Sun-Chieh Chien ,  King-Lung Wu ,  Chuan-Fu Wang ,  Jason Jenq

发明人： Sun-Chieh Chien ,  King-Lung Wu ,  Chuan-Fu Wang ,  Jason Jenq

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.

摘要翻译： 提供一种用于制造DRAM电容器的方法，以通过使用第一级和第二级形成具有圆柱形轮廓的下电极。 这些阶段在各种情况下提供不同的蚀刻速率。 本发明使用这些阶段来允许电容器之间的第二多晶硅层的一部分被完全蚀刻，并且防止用作下部电极的第二多晶硅层的另一部分过度蚀刻。 本发明提供了形成具有更大表面的圆柱形电容器的更容易的工艺。

公开(公告)号：US5985709A

公开(公告)日：1999-11-16

申请号：US962116

申请日：1997-10-31

申请人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsu

发明人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsu

IPC分类号： H01L21/8238 ,  H01L21/8244 ,  H01L29/68

CPC分类号： H01L27/11 ,  H01L21/823892

摘要： A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.

摘要翻译： 用于诸如SRAM IC器件的半导体IC器件的三阱结构及其制造方法，其允许改进的数据存储稳定性以及针对来自设备I / O弹跳和α粒子的干扰的改进的抗扰性能力。 三阱结构包括P型底物中的至少一个P阱，多个N阱和在N个孔内形成的逆行P阱。 制造三阱结构的工艺包括首先在P型衬底中注入硼离子。 随后形成用于在要制造P型MOS晶体管的区域中注入磷离子的光掩模。 然后采用高温驱动程序来形成P阱和多个N阱。 然后对定义有N型MOS晶体管的N阱中的一个选择区域进行硼离子注入，然后进行退火程序以形成逆行P阱。

公开(公告)号：US5924007A

公开(公告)日：1999-07-13

申请号：US910999

申请日：1997-08-14

申请人： Chia-Wen Liang ,  Jason Jenq ,  Chuan-Fu Wang ,  Sun-Chieh Chien

发明人： Chia-Wen Liang ,  Jason Jenq ,  Chuan-Fu Wang ,  Sun-Chieh Chien

IPC分类号： H01L21/321 ,  H01L21/469

CPC分类号： H01L21/321

摘要： A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.

摘要翻译： 一种改善多晶硅介电层平坦化的方法。 在形成多晶硅层的半导体器件上，通过使用气氛化学气相沉积，形成未掺杂的多晶硅间介质层。 在未掺杂的多晶硅间介质层上形成掺杂的多晶硅介电层。 在高温下，对掺杂的多晶硅介电层进行回流和回蚀作业。 在形成第二多晶硅层之前，进行快速热处理。

公开(公告)号：US5888866A

公开(公告)日：1999-03-30

申请号：US75098

申请日：1998-05-08

申请人： Sun-Chieh Chien

发明人： Sun-Chieh Chien

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating capacitors of a DRAM by employing the liquid-phase deposition. Since the working temperature required for performing liquid-phase deposition is low, selective deposition can be performed on the area not covered by photoresist with the presence of the photoresist layer. The foregoing method comprises: filling up the contact hole with photoresist, and keeping up coating photoresist upward and horizontally; selectively depositing oxide on the area, that is not coated with photoresist, by utilizing the liquid-phase deposition process; removing the photoresist for forming an opening which forms the profile of the lower electrode of a capacitor; forming a conductive layer on the inner walls of the opening, and having the contact hole filled as well to form the lower electrode.

摘要翻译： 一种通过采用液相沉积制造DRAM的电容器的方法。 由于进行液相沉积所需的工作温度低，所以可以在存在光致抗蚀剂层的情况下对未被光致抗蚀剂覆盖的区域进行选择性沉积。 上述方法包括：用光致抗蚀剂填充接触孔，并且上下水平地保持涂层光致抗蚀剂; 通过利用液相沉积工艺选择性地在该区域上沉积氧化物，其中未涂覆有光致抗蚀剂; 去除用于形成开口的光致抗蚀剂，其形成电容器的下电极的轮廓; 在开口的内壁上形成导电层，并且还具有填充的接触孔以形成下电极。

公开(公告)号：US5872055A

公开(公告)日：1999-02-16

申请号：US768971

申请日：1996-12-18

申请人： Jason Jenq ,  Sun-Chieh Chien

发明人： Jason Jenq ,  Sun-Chieh Chien

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L21/32139 ,  H01L21/32134 ,  H01L21/76885

摘要： A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.

摘要翻译： 一种制造适用于集成电路的多晶硅导线的制造方法，其可以避免在光刻处理期间由紫外光的反射引起的图案转移误差，并且导致部分导电磨损的宽度缩窄或瓶颈效应。 在具有预成型器件的半导体衬底之上形成多晶硅层。 在多晶硅层上方形成帽绝缘层。 在帽绝缘层的表面上形成微粗糙结构。 将光致抗蚀剂层涂覆在帽绝缘层的微粗糙表面上。 通过选择性曝光然后去除未曝光的光致抗蚀剂将图案转印到光致抗蚀剂层上。 然后在未被光致抗蚀剂覆盖的区域中依次蚀刻帽绝缘层和多晶硅层。 然后去除剩余光致抗蚀剂留下多晶硅导电线。

公开(公告)号：US5413945A

公开(公告)日：1995-05-09

申请号：US289671

申请日：1994-08-12

申请人： Sun-Chieh Chien ,  Tzong-Shien Wu

发明人： Sun-Chieh Chien ,  Tzong-Shien Wu

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L27/0928 ,  H01L21/823807

摘要： A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures. The P-well region is implanted, in a substantially vertical direction, with a fourth conductivity-imparting dopant, of the same conductivity as the second conductivity-imparting dopant. The N-well region is implanted, in a substantially vertical direction, with a fifth conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. The silicon substrate is heated to drive in the dopants.

摘要翻译： 描述了一种制造不受热载流子效应的亚微米MOS（金属氧化物半导体）器件的方法，并且具有改善的短沟道效应和改进的性能。 提供了具有场隔离区域的硅衬底，P阱和N阱区域以及P阱和N阱区域上的氧化物层。 P阱区域在基本上垂直的方向上用第一导电性掺杂剂注入。 栅极结构形成在P阱和N阱区上。 第二导电性赋予掺杂剂以与第一导电性赋予掺杂剂相反的导电性的方式与硅衬底的平面成大角度地注入由P阱和N阱区域掩蔽的栅极结构 。 N阱区域在基本上垂直的方向上与具有与第一导电性赋予掺杂剂相同的导电性的第三导电性赋予掺杂剂注入。 侧壁间隔件形成在栅极结构上。 P阱区域在基本上垂直的方向上与第四导电性赋予掺杂剂一样，与第二导电性赋予掺杂剂相同。 在基本上垂直的方向上，用具有与赋予第一导电性的掺杂剂相同的导电性的第五导电性掺杂剂将N阱区域注入。 硅衬底被加热以在掺杂剂中驱动。