Methods and Apparatus for Velocity Detection in MIMO Radar Including Velocity Ambiguity Resolution

    公开(公告)号:US20180011170A1

    公开(公告)日:2018-01-11

    申请号:US15371754

    申请日:2016-12-07

    Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

    METHOD AND APPARATUS FOR GNSS SIGNAL TRACKING

    公开(公告)号:US20170285173A1

    公开(公告)日:2017-10-05

    申请号:US15629860

    申请日:2017-06-22

    CPC classification number: G01S19/246 G01S19/29

    Abstract: A GNSS receiver to track low power GNSS satellite signals. The GNSS receiver includes a frequency locked loop (FLL) that measures a current doppler frequency of the satellite signal. A delay locked loop (DLL) measures a current code phase delay of the satellite signal. A current operating point corresponds to the current doppler frequency and the current code phase delay of the satellite signal. A grid monitor receives the satellite signal and the current operating point, and measures a satellite signal strength at a plurality of predefined offset points from the current operating point. The FLL and the DLL are centered at the current operating point. A peak detector is coupled to the grid monitor and processes the satellite signal strengths at the plurality of predefined offset points and re-centers the FLL and the DLL to a predefined offset point with the satellite signal strength above a predefined threshold.

    CHIRP FREQUENCY NON-LINEARITY MITIGATION IN RADAR SYSTEMS
    75.
    发明申请
    CHIRP FREQUENCY NON-LINEARITY MITIGATION IN RADAR SYSTEMS 审中-公开
    雷达系统中的CHIRP频率非线性缓解

    公开(公告)号:US20170045607A1

    公开(公告)日:2017-02-16

    申请号:US14826045

    申请日:2015-08-13

    Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

    Abstract translation: 本公开提供了一种雷达装置。 雷达装置包括响应于参考时钟和反馈时钟产生第一信号的发射单元。 第一信号被一个或多个障碍物分散以产生第二信号。 接收单元接收第二信号并产生对应于第二信号的N个采样。 N是整数。 调理电路耦合到发送单元和接收单元。 调理电路接收对应于第二信号的N个采样,并且使用反馈时钟和参考时钟之间的误差来生成N个新采样。

    Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency
    76.
    发明授权
    Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency 有权
    二进制频移键控,数字调制和数据转换,从中频生成载波

    公开(公告)号:US09401702B2

    公开(公告)日:2016-07-26

    申请号:US14250880

    申请日:2014-04-11

    CPC classification number: H03K7/06 H04L27/10 H04L27/12 H04L27/127

    Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

    Abstract translation: 通过选择高频时钟的适当相位来产生调制的中间时钟频率来实现二进制频移键控调制。 高频时钟选择为(M + 0.5)* fc,其中fc是载波频率,M是整数。 根据要发送的二进制数据'1'或'0',来自高频时钟的“M”或“M + 1”个时钟相位被转换为比载波频率快2倍N倍的中间时钟, 其中N是整数。 该完全在数字域中产生的中间时钟在其中具有所需的数据调制,并用于产生以载波频率工作的N个脉宽调制(PWM)相位。 然后适当地称重N相,以合成基本上抑制其低次谐波的正弦波形。

    Mitigation of spurious signals in GNSS receivers
    77.
    发明授权
    Mitigation of spurious signals in GNSS receivers 有权
    减少GNSS接收机中的杂散信号

    公开(公告)号:US09395444B2

    公开(公告)日:2016-07-19

    申请号:US13906104

    申请日:2013-05-30

    CPC classification number: G01S19/21

    Abstract: A method of processing received satellite signals is provided. The method includes detecting frequency, power level, code phase and doppler frequency of a plurality of satellite signals and frequency and power level of a plurality of spurious signals. The plurality of spurious signals is ranked based on one or more ranking parameters. A first subset of the plurality of spurious signals which are ranked equal or above a threshold rank are processed through a plurality of notch filters and a second subset of the plurality of spurious signals which are ranked below the threshold rank are processed through a weeding filter.

    Abstract translation: 提供一种处理接收到的卫星信号的方法。 该方法包括检测多个卫星信号的频率,功率电平,码相位和多普勒频率以及多个寄生信号的频率和功率电平。 基于一个或多个排序参数对多个假信号进行排名。 排列等于或高于阈值秩的多个寄生信号的第一子集通过多个陷波滤波器进行处理,并且通过除草滤波器处理排列在阈值级别之下的多个杂散信号的第二子集。

    Controlling Radar Transmission to Enable Interference Mitigation
    78.
    发明申请
    Controlling Radar Transmission to Enable Interference Mitigation 有权
    控制雷达传输以实现干扰减轻

    公开(公告)号:US20160146933A1

    公开(公告)日:2016-05-26

    申请号:US14552505

    申请日:2014-11-25

    Abstract: Radar detection of an object is achieved by identifying a first range associated with a possible object based on a first return from a first radar transmission having a first chirp rate, and identifying a second range associated with the possible object based on a second return from a second radar transmission having a second chirp rate that differs from the first chirp rate. The first and second ranges are evaluated together to determine whether the possible object is a true object.

    Abstract translation: 通过基于来自具有第一啁啾率的第一雷达传输的第一返回来识别与可能对象相关联的第一范围,并且基于来自第一啁啾率的第二返回来识别与可能对象相关联的第二范围来实现对象的雷达检测 第二雷达传输具有与第一啁啾率不同的第二啁啾率。 一起评估第一和第二范围以确定可能的对象是否是真实对象。

    Radar system implementing segmented chirps and phase compensation for object movement

    公开(公告)号:US12248091B2

    公开(公告)日:2025-03-11

    申请号:US17486435

    申请日:2021-09-27

    Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B′), and concatenate M2(A) and M2(B′) to obtain an aggregate velocity matrix M2(A&B′). The processor cores perform a second FT on each row of M2(A&B′) to obtain a range and velocity matrix M3(A&B′).

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