公开(公告)号：US11670723B2

公开(公告)日：2023-06-06

申请号：US17097323

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  H01L21/0262 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

公开(公告)号：US11670692B2

公开(公告)日：2023-06-06

申请号：US17218503

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes power rails in a first interconnect structure on a backside of the semiconductor device. The semiconductor device further includes a gate-all-around (GAA) transistor having multiple channel layers stacked over the first interconnect structure, a gate stack wrapping around each of the multiple channel layers except a bottommost one of the multiple channel layers, and a source/drain feature adjoining the channel layers. The semiconductor device further includes a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature and a dielectric feature isolating the bottommost one of the multiple channel layers from the first conductive via.

公开(公告)号：US11594614B2

公开(公告)日：2023-02-28

申请号：US16834637

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L21/82 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

公开(公告)号：US20220278224A1

公开(公告)日：2022-09-01

申请号：US17663979

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US11374105B2

公开(公告)日：2022-06-28

申请号：US16835759

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

公开(公告)号：US11245033B2

公开(公告)日：2022-02-08

申请号：US16049358

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. Diaz ,  Chun-Hsiung Lin ,  Huicheng Chang ,  Syun-Ming Jang ,  Chien-Hsun Wang ,  Mao-Lin Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

公开(公告)号：US11201094B2

公开(公告)日：2021-12-14

申请号：US16372021

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3115 ,  H01L27/092 ,  H01L21/8234

Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.

公开(公告)号：US11145734B1

公开(公告)日：2021-10-12

申请号：US16915784

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; a gate structure wrapping each of the semiconductor layers; a spacer structure wrapping an edge portion of each of the semiconductor layers; and a dummy fin structure contacting a sidewall of the gate structure, wherein the dummy fin structure is separated from a sidewall of the spacer structure by a dielectric liner.

公开(公告)号：US20200043919A1

公开(公告)日：2020-02-06

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.