公开(公告)号：US08243517B2

公开(公告)日：2012-08-14

申请号：US12730330

申请日：2010-03-24

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

公开(公告)号：US08213232B2

公开(公告)日：2012-07-03

申请号：US13210431

申请日：2011-08-16

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

摘要翻译： 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US20120137961A1

公开(公告)日：2012-06-07

申请号：US13315871

申请日：2011-12-09

申请人： Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka ,  Naoya Miyoshi

发明人： Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka ,  Naoya Miyoshi

IPC分类号： C30B11/06

CPC分类号： C30B29/403 ,  C30B9/10 ,  C30B35/002

摘要： Materials of a nitride single crystal of a metal belonging to III group and a flux are contained in a crucible, which is contained in a reaction container, the reaction container is contained in an outer container, the outer container is contained in a pressure container, and nitrogen-containing atmosphere is supplied into the outer container and melt is generated in the crucible to grow a nitride single crystal of a metal belonging to III group. The reaction container includes a main body containing the crucible and a lid. The main body includes a side wall having a fitting face and a groove opening at the fitting face and a bottom wall. The lid has an upper plate part including a contact face for the fitting face of the main body and a flange part extending from the upper plate part and surrounding an outer side of said side wall.

摘要翻译： 属于III族的金属的氮化物单晶和助熔剂的材料包含在容纳在反应容器中的坩埚中，反应容器容纳在外容器中，外容器容纳在压力容器中， 向外容器供给含氮气氛，在坩埚中产生熔融物，生长属于III族的金属的氮化物单晶。 反应容器包括容纳坩埚和盖的主体。 主体包括具有配合面的侧壁和在配合面处的槽开口和底壁。 盖具有上板部，其包括用于主体的嵌合面的接触面和从上板部延伸并围绕所述侧壁的外侧的凸缘部。

公开(公告)号：US08039561B2

公开(公告)日：2011-10-18

申请号：US10533169

申请日：2003-10-28

申请人： Takeaki Saiki ,  Makoto Iwai

发明人： Takeaki Saiki ,  Makoto Iwai

IPC分类号： C08F283/00 ,  C08F283/06 ,  C08G75/04 ,  C08L81/02 ,  C08G77/60

CPC分类号： C08G77/28 ,  C07F7/1804 ,  C08G75/14 ,  C08G77/42

摘要： To provide a highly efficient and stable method for the preparation of a silicon-containing polysulfide-type polymer, in particular, a polysulfide-type polymer with organosilyl groups, the method being carried out without generation of by-products that could have high impact on the environment. A method for the preparation of a silicon-containing polysulfide-type polymer characterized by mixing (A) a silicon-containing compound having a silicon atom-bonded monovalent organic group having an aliphatic unsaturated bond; (B) a polysulfide polymer with at least two mercapto groups in one molecule; and (C) an organic base or ammonia; the mixing being carried out in the presence of (D) sulfur.

摘要翻译： 为了提供用于制备含硅多硫化物型聚合物，特别是具有有机甲硅烷基的多硫化物型聚合物的高效稳定的方法，该方法是在不产生可能对 环境。 一种制备含硅多硫化物型聚合物的方法，其特征在于混合（A）具有硅原子键合的具有脂族不饱和键的一价有机基团的含硅化合物; （B）在一个分子中具有至少两个巯基的多硫化物聚合物; 和（C）有机碱或氨; 在（D）硫的存在下进行混合。

公开(公告)号：US08036038B2

公开(公告)日：2011-10-11

申请号：US12951616

申请日：2010-11-22

申请人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

发明人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括 多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且 使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度 其他在字线方向。

公开(公告)号：US08009470B2

公开(公告)日：2011-08-30

申请号：US12563296

申请日：2009-09-21

申请人： Makoto Iwai ,  Hiroshi Nakamura

发明人： Makoto Iwai ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。

公开(公告)号：US07995389B2

公开(公告)日：2011-08-09

申请号：US12563274

申请日：2009-09-21

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

摘要： A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，串联连接在第一和第二选择栅极晶体管之间的存储单元，连接到所选存储单元作为读取目标的选定字线，未被选择的字 线路，其连接到除所选择的存储器单元之外的未选择的存储器单元;电位产生电路，用于产生提供给所选择的字线的所选择的读取电位，以及产生大于所选择的读取电位的未选择的读取电位 ，其被提供给未选择的字线，以及控制电路，其基于所选择的读取电位的值来改变所选字线和未选择的字线的设置项，其中所选择的 从两个或更多个电位中选择读取电位。

公开(公告)号：US07859901B2

公开(公告)日：2010-12-28

申请号：US12329007

申请日：2008-12-05

申请人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

发明人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括 多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且 使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度 其他在字线方向。

公开(公告)号：US20100177563A1

公开(公告)日：2010-07-15

申请号：US12730330

申请日：2010-03-24

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/04 ,  G11C16/02

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

摘要翻译： 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US20100135078A1

公开(公告)日：2010-06-03

申请号：US12563296

申请日：2009-09-21

申请人： Makoto Iwai ,  Hiroshi Nakamura

发明人： Makoto Iwai ,  Hiroshi Nakamura

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。