公开(公告)号：US06956758B2

公开(公告)日：2005-10-18

申请号：US11049463

申请日：2005-02-03

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C8/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

摘要翻译： 复合栅极根据复合栅极的输出信号与地址转换检测信号之间的定时关系，检测内部阵列是处于选择状态还是内部行激活信号被激活。 当应用地址转换检测信号时，根据指示内部阵列是否处于选择状态的延迟恢复周期信号的产生定时和地址转换检测信号来允许下一行访问，内部行激活信号被去激活。 通过这样的配置，允许在内部状态确定地恢复到初始状态之后开始下一个操作。 当在恢复操作期间应用下一个地址转换检测信号，列恢复操作或刷新操作时，数据访问被正确地执行而不会导致数据破坏。

公开(公告)号：US06714047B2

公开(公告)日：2004-03-30

申请号：US10266757

申请日：2002-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

IPC分类号： H03K190185

CPC分类号： H03K19/018585 ,  H03K19/00384

摘要： The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.

摘要翻译： 半导体集成电路包括接收信号的输入电路，对接收信号施加预定功能的内部电路以及输出施加了预定功能的信号的输出电路。 将低于电压VDD的外部电源电压VDD和IO电源电压VDDQ提供给半导体集成电路。 通过降低外部电源电压VDD获得的电压VIO被提供给输入电路。 IO电源电压VDDQ被提供给输出电路。

公开(公告)号：US06697910B2

公开(公告)日：2004-02-24

申请号：US09987895

申请日：2001-11-16

申请人： Masaki Tsukude ,  Shinichi Kobayashi ,  Hirotoshi Sato

发明人： Masaki Tsukude ,  Shinichi Kobayashi ,  Hirotoshi Sato

IPC分类号： G06F1200

CPC分类号： G11C11/406

摘要： In a semiconductor memory device, a refresh circuit outputs a refresh command signal for executing refresh operation. The refresh circuit includes a command-signal activating circuit for activating the refresh command signal, and a determination circuit for determining whether the activated refresh command signal is to be output. The determination circuit determines that the activated refresh command signal is to be output when the semiconductor memory device is in a standby state. Thereby, the semiconductor memory device enables stable refresh operation to be executed.

摘要翻译： 在半导体存储器件中，刷新电路输出用于执行刷新操作的刷新命令信号。 刷新电路包括用于激活刷新命令信号的命令信号激活电路，以及用于确定是否输出激活的刷新命令信号的确定电路。 确定电路确定当半导体存储器件处于待机状态时，输出激活的刷新命令信号。 因此，半导体存储器件能够执行稳定的刷新操作。

公开(公告)号：US06628559B2

公开(公告)日：2003-09-30

申请号：US09971694

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

公开(公告)号：US06501693B2

公开(公告)日：2002-12-31

申请号：US09986874

申请日：2001-11-13

申请人： Takafumi Takatsuka ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Masaki Tsukude

IPC分类号： G11C2900

CPC分类号： G11C11/406 ,  G11C29/50

摘要： A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.

摘要翻译： 行控制电路包括：选择器，用于根据测试信号TEST作为信号ZRXTRSTD输出信号INTSIG或ZRXTRST;以及保持电路，用于通过输入A接收信号ZRXTS，由输入端B接收信号ZRXTRSTD 并从输出节点OUT输出字线激活信号RXT。 在测试模式中，读出放大器激活信号S0N和字线有效信号RXT的相位关系被设置为与正常模式不同。 因此，可以评估读取操作或恢复操作的定时的余量。

公开(公告)号：US06493279B2

公开(公告)日：2002-12-10

申请号：US09972243

申请日：2001-10-09

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Tadayuki Shimizu

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Tadayuki Shimizu

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.

摘要翻译： 在测试模式中，第一开关电路被去激活，第二和第三开关电路被激活。 环形振荡器的振荡频率可以通过测量从输入测试信号的节点的信号到通过第二开关电路输出的时间的延迟值，反相和延迟电路以及第三开关电路 。 因此，可以提供能够简单测量振荡频率的半导体器件。

公开(公告)号：US06434065B1

公开(公告)日：2002-08-13

申请号：US09911729

申请日：2001-07-25

申请人： Shinichi Kobayashi ,  Masaki Tsukude

发明人： Shinichi Kobayashi ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C7/12 ,  G11C29/02 ,  G11C2207/2227

摘要： In order to change the precharging voltage level when the bit lines are in the floating state, current control circuits are provided for restricting a current supply amount to the bit lines in the standby state, for example. Data, of which the logic level is fixed, are read out, in the existence of a leak current, due to a change of the bit line voltage caused by this leak current and thereby, the existence of a minute leak current can be detected. Consequently, a semiconductor memory device with an extremely low standby current is implemented by precisely detecting a minute leak current of the bit lines and by repairing the leak current defect.

摘要翻译： 为了在位线处于浮置状态时改变预充电电压电平，例如提供电流控制电路用于限制待机状态下的位线的电流供给量。 由于漏电流引起的位线电压的变化，在存在漏电流的情况下，读出固定有逻辑电平的数据，从而可以检测出微小漏电流的存在。 因此，具有极低待机电流的半导体存储器件通过精确检测位线的微小泄漏电流并修复泄漏电流缺陷来实现。

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US6134171A

公开(公告)日：2000-10-17

申请号：US317860

申请日：1999-05-25

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L27/105 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

公开(公告)号：US6075732A

公开(公告)日：2000-06-13

申请号：US334917

申请日：1999-06-17

申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC分类号： G11C29/806 ,  G11C29/781 ,  G11C8/10

摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。