公开(公告)号：US06584013B2

公开(公告)日：2003-06-24

申请号：US09982792

申请日：2001-10-22

申请人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

发明人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

IPC分类号： G11C1134

CPC分类号： G11C11/005

摘要： A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

公开(公告)号：US06628559B2

公开(公告)日：2003-09-30

申请号：US09971694

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

公开(公告)号：US06737906B2

公开(公告)日：2004-05-18

申请号：US09986871

申请日：2001-11-13

申请人： Minoru Senda ,  Masaki Tsukude

发明人： Minoru Senda ,  Masaki Tsukude

IPC分类号： G05F110

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.

摘要翻译： 在操作中，电荷泵浦电路向内部电压线提供负电荷以便减小负的内部电压。 分压电路根据外部施加到测试模式中的第一输入端子的第一正电压与内部电压之间的差产生控制电压。 比较电路根据外部施加到测试模式中的第二输入端子的第二正电压与控制电压之间的比较结果来操作电荷泵送电路。 第二正电压根据负内部电压的目标值设定。

公开(公告)号：US06556485B2

公开(公告)日：2003-04-29

申请号：US09972242

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

公开(公告)号：US06798236B2

公开(公告)日：2004-09-28

申请号：US10271799

申请日：2002-10-17

申请人： Tadayuki Shimizu ,  Takafumi Takatsuka ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Takafumi Takatsuka ,  Masaki Tsukude

IPC分类号： H03K19003

CPC分类号： H03K19/0016 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

摘要翻译： 一种半导体集成电路，其从外部提供第一电源电压和第二电源电压，以便操作并入的电路，并且在输出端子处输出数据，包括执行用于输入信号的预定功能的内部电路 输出电路，其包括用于将来自内部电路的信号转换为输出信号的第一电路和包含最终级缓冲电路的第二电路，其根据来自第一电路的信号将数据输出到输出端; 以及将提供给第二电路的电源电压切换到第一电源电压或第二电源电压的开关电路。 通过减小第一电源电压获得的电压被提供给内部电路。 第一电源电压被提供给第一电路。

公开(公告)号：US06714047B2

公开(公告)日：2004-03-30

申请号：US10266757

申请日：2002-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

IPC分类号： H03K190185

CPC分类号： H03K19/018585 ,  H03K19/00384

摘要： The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.

摘要翻译： 半导体集成电路包括接收信号的输入电路，对接收信号施加预定功能的内部电路以及输出施加了预定功能的信号的输出电路。 将低于电压VDD的外部电源电压VDD和IO电源电压VDDQ提供给半导体集成电路。 通过降低外部电源电压VDD获得的电压VIO被提供给输入电路。 IO电源电压VDDQ被提供给输出电路。

公开(公告)号：US06493279B2

公开(公告)日：2002-12-10

申请号：US09972243

申请日：2001-10-09

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Tadayuki Shimizu

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Tadayuki Shimizu

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.

摘要翻译： 在测试模式中，第一开关电路被去激活，第二和第三开关电路被激活。 环形振荡器的振荡频率可以通过测量从输入测试信号的节点的信号到通过第二开关电路输出的时间的延迟值，反相和延迟电路以及第三开关电路 。 因此，可以提供能够简单测量振荡频率的半导体器件。

公开(公告)号：US06707735B2

公开(公告)日：2004-03-16

申请号：US10120445

申请日：2002-04-12

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

摘要翻译： 当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。 通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。 提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

公开(公告)号：US06590823B2

公开(公告)日：2003-07-08

申请号：US09988172

申请日：2001-11-19

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

公开(公告)号：US06341098B2

公开(公告)日：2002-01-22

申请号：US09846223

申请日：2001-05-02

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。