公开(公告)号：US20080272837A1

公开(公告)日：2008-11-06

申请号：US11930804

申请日：2007-10-31

申请人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

发明人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC分类号： H03K5/00

CPC分类号： H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

摘要翻译： 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US07376399B2

公开(公告)日：2008-05-20

申请号：US11096134

申请日：2005-03-31

申请人： David R. Welland ,  Caiyi Wang

发明人： David R. Welland ,  Caiyi Wang

IPC分类号： H04B1/04 ,  H03C3/02 ,  H04B1/40

CPC分类号： H04B1/403

摘要： Mixing circuitry for quadrature processing in communication systems and related methods are disclosed. The weighted mixing circuitry allows for arbitrary dividers to be utilized in generating the mixing signals for quadrature processing and thereby provides a significant advantage over prior architectures where 90 degree offset I and Q mixing signals were needed for quadrature mixing.

摘要翻译： 公开了用于通信系统中的正交处理的混合电路及相关方法。 加权混合电路允许任意的分频器用于生成用于正交处理的混合信号，并且因此提供了相对于其中需要90度偏移I和Q混合信号以进行正交混合的现有架构的显着优点。

公开(公告)号：US07283584B2

公开(公告)日：2007-10-16

申请号：US10780142

申请日：2004-02-17

申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

公开(公告)号：US07262725B2

公开(公告)日：2007-08-28

申请号：US11461408

申请日：2006-07-31

申请人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

发明人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

IPC分类号： H03M1/00

CPC分类号： H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

摘要翻译： 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US07072389B2

公开(公告)日：2006-07-04

申请号：US10227104

申请日：2002-08-23

申请人： Jeffrey W. Scott ,  Navdeep S Sooch ,  David R. Welland

发明人： Jeffrey W. Scott ,  Navdeep S Sooch ,  David R. Welland

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

公开(公告)号：US06993314B2

公开(公告)日：2006-01-31

申请号：US10074591

申请日：2002-02-13

申请人： Lysander Lim ,  Caiyi Wang ,  David R. Welland ,  Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu S. Srinivasan

发明人： Lysander Lim ,  Caiyi Wang ,  David R. Welland ,  Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu S. Srinivasan

IPC分类号： H04N1/28

CPC分类号： H04B1/0003 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/28 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064

摘要： A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.

公开(公告)号：US06975723B2

公开(公告)日：2005-12-13

申请号：US10429795

申请日：2003-05-05

申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland ,  Jerrell P. Hein ,  Andrew W. Krone

发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland ,  Jerrell P. Hein ,  Andrew W. Krone

IPC分类号： H03M1/42 ,  H04L7/033 ,  H04L25/02 ,  H04L25/06 ,  H04M1/57 ,  H04M11/06 ,  H04M19/00 ,  H04M19/02 ,  H04M1/00 ,  H04M9/00

CPC分类号： H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

摘要： A communication system is provided which draws virtually no loop current during a ringing burst and only draws on-hook loop current during the caller ID field. More particularly, ringer burst circuitry may be powered from the user powered circuitry by the transmission of power across the isolation barrier rather than being powered from the phone line. Thus, loop current need not be drawn from the TIP/RING lines during ringer bursts. The isolation barrier may be a capacitive isolation barrier which allows bidirectional communication and extraction of power from signals transmitted across the barrier.

摘要翻译： 提供一种通信系统，其在振铃突发期间几乎不消除环路电流，并且仅在呼叫者ID字段期间吸引挂机环路电流。 更具体地，振铃突发电路可以由用户供电的电路通过跨隔离屏障的功率传输而不是从电话线供电。 因此，在振铃器脉冲串期间，不需要从TIP / RING线路中抽出回路电流。 隔离屏障可以是电容隔离屏障，其允许通过屏障传输的信号的双向通信和功率提取。

公开(公告)号：US06823066B1

公开(公告)日：2004-11-23

申请号：US09347689

申请日：1999-07-02

申请人： George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

发明人： George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC分类号： H04M100

CPC分类号： H04L25/0266 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06 ,  H04M19/001

摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper hookswitch transition for a variety of international phone standards is provided. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DAA circuitry may be utilized which satisfies many or all hookswitch transition standards without the use of additional discrete devices. The hookswitch transition standards may be satisfied by ramping down the current flowing through the hookswitch prior to transitioning the hookswitch state. In this manner the hookswitch current change as a function of time (di/dt) may be decreased. Thus, the current through the hookswitch may be actively controlled prior to switching the hookswitch from an off-hook condition to an on-hook condition. By controlling the current drawn from the phone lines through the hookswitch, the maximum voltage seen at the phone company exchange may be decreased.

公开(公告)号：US06611553B1

公开(公告)日：2003-08-26

申请号：US09591684

申请日：2000-06-09

申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC分类号： H04M318

CPC分类号： H04L25/0266 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06

摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

公开(公告)号：US06574288B1

公开(公告)日：2003-06-03

申请号：US09087012

申请日：1998-05-29

申请人： David R. Welland ,  Caiyi Wang

发明人： David R. Welland ,  Caiyi Wang

IPC分类号： H04B106

CPC分类号： H03L7/199 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/113

摘要： A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, discrete control circuitry is disclosed that provides a digital control signal to a discretely variable capacitance circuit to control its overall capacitance and that adjusts the digital control signal depending upon feedback from the output frequency.

摘要翻译： 公开了一种用于合成高频信号的方法和装置，其克服了与现有实施相关的集成问题，同时满足苛刻的相位噪声和其他杂质要求。 在一个实施例中，公开了具有可变电容的压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容包括连续可变电容的离散可变电容。 离散可变电容可以提供可变电容的粗调谐调节，并且连续可变电容可以提供可变电容的精细调谐。 更详细地，公开了离散控制电路，其向离散可变电容电路提供数字控制信号以控制其整体电容，并且根据来自输出频率的反馈来调整数字控制信号。