中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

151 records (took 0.032 seconds)

    Method and apparatus for reducing interference
    2.
    发明授权
    Method and apparatus for reducing interference 有权
    减少干扰的方法和装置

    公开(公告)号：US08154336B2

    公开(公告)日：2012-04-10

    申请号：US11930596

    申请日：2007-10-31

    Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    IPC: H03K5/00

    CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

    Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

    Histogram-based automatic gain control method and system for video applications
    4.
    发明授权
    Histogram-based automatic gain control method and system for video applications 有权
    基于直方图的自动增益控制方法和视频应用系统

    公开(公告)号：US07522193B2

    公开(公告)日：2009-04-21

    申请号：US10862488

    申请日：2004-06-07

    Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

    Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

    IPC: H04N5/235 ,  H04N5/228 ,  H04N5/217

    CPC classification number: H04N5/2352

    Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

    Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

    Correlated double sampling variable gain amplifier circuit for use in a digital camera
    5.
    发明授权
    Correlated double sampling variable gain amplifier circuit for use in a digital camera 有权
    用于数码相机的相关双倍可变增益放大器电路

    公开(公告)号：US07289145B2

    公开(公告)日：2007-10-30

    申请号：US11415000

    申请日：2006-05-01

    Applicant: Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

    Inventor： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

    IPC: H04N5/235

    CPC classification number: H04N5/3575 ,  H04N5/335 ,  H04N5/361

    Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

    Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路 所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。 处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。

    Phase locked loop circuitry for synthesizing high-frequency signals and associated method
    7.
    发明授权
    Phase locked loop circuitry for synthesizing high-frequency signals and associated method 有权
    用于合成高频信号和相关方法的锁相环电路

    公开(公告)号：US06549765B2

    公开(公告)日：2003-04-15

    申请号：US09933530

    申请日：2001-08-20

    Applicant: David R. Welland ,  Caiyi Wang

    Inventor： David R. Welland ,  Caiyi Wang

    IPC: H04B126

    CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

    Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

    Method and apparatus for reducing interference
    8.
    发明授权
    Method and apparatus for reducing interference 有权
    减少干扰的方法和装置

    公开(公告)号：US08648653B2

    公开(公告)日：2014-02-11

    申请号：US12650546

    申请日：2009-12-31

    Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    IPC: H03K5/00

    CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

    Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

    Ratiometric transmit path architecture for communication systems
    10.
    发明授权
    Ratiometric transmit path architecture for communication systems 有权
    通信系统的比例传输路径架构

    公开(公告)号：US07376396B2

    公开(公告)日：2008-05-20

    申请号：US11096133

    申请日：2005-03-31

    Applicant: David R. Welland ,  Caiyi Wang

    Inventor： David R. Welland ,  Caiyi Wang

    IPC: H04B1/40 ,  H03C1/52

    CPC classification number: H04B1/403

    Abstract: A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.

    Abstract translation: 公开了用于通信系统和相关方法的比例传输路径架构。 这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要 以前的解决方案。

Patent Agency Ranking