公开(公告)号：US07262725B2

公开(公告)日：2007-08-28

申请号：US11461408

申请日：2006-07-31

申请人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

发明人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

IPC分类号： H03M1/00

CPC分类号： H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

摘要翻译： 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US07084710B2

公开(公告)日：2006-08-01

申请号：US10998521

申请日：2004-11-29

申请人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

发明人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

IPC分类号： H03L7/099

CPC分类号： H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

摘要翻译： 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US09095041B2

公开(公告)日：2015-07-28

申请号：US11930804

申请日：2007-10-31

申请人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

发明人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC分类号： H03K5/00 ,  H05K9/00 ,  H03L7/18 ,  H05K1/02 ,  H05K3/10

CPC分类号： H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US20120169659A1

公开(公告)日：2012-07-05

申请号：US13335407

申请日：2011-12-22

申请人： David R. Welland

发明人： David R. Welland

IPC分类号： G06F3/045

CPC分类号： G06F3/044 ,  G06F3/0416

摘要： A method for interfacing with a capacitive touch screen is disclosed. The method includes charging an internal capacitor in the touch screen, which internal capacitor is disposed proximate a fixed location on the touch screen and is capable of changing in response to a touch at that location on the touch screen. After charging, value of the charge on the internal capacitor is determined in a manner to reduce effects of interference.

摘要翻译： 公开了一种用于与电容式触摸屏接口的方法。 该方法包括对触摸屏中的内部电容器进行充电，该内部电容器设置在触摸屏上的固定位置附近，并且能够响应于触摸屏上该位置处的触摸而改变。 充电后，以减少干扰影响的方式确定内部电容器的电荷值。

公开(公告)号：US08154336B2

公开(公告)日：2012-04-10

申请号：US11930596

申请日：2007-10-31

申请人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

发明人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC分类号： H03K5/00

CPC分类号： H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

摘要翻译： 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US20100102876A1

公开(公告)日：2010-04-29

申请号：US12650545

申请日：2009-12-31

申请人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

发明人： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC分类号： H03B1/04

CPC分类号： H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US07522193B2

公开(公告)日：2009-04-21

申请号：US10862488

申请日：2004-06-07

申请人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

发明人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC分类号： H04N5/235 ,  H04N5/228 ,  H04N5/217

CPC分类号： H04N5/2352

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US07515672B2

公开(公告)日：2009-04-07

申请号：US10679013

申请日：2003-10-03

申请人： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

发明人： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC分类号： H04L23/00

CPC分类号： H04L25/06 ,  H04L7/033 ,  H04L25/0266 ,  H04M11/06 ,  H04M19/001

摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable circuit for the DC termination for a variety of international phone standards. The invention may also be utilized with circuitry for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

摘要翻译： 可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。 简要描述，DAA为各种国际电话标准的DC终端提供可编程电路。 本发明还可以用于跨电容隔离屏障发送和接收信号的电路。 更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。 在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。 此外，大部分功率可能会在外部无源器件（如电阻）中消散。

公开(公告)号：US07362841B2

公开(公告)日：2008-04-22

申请号：US10292290

申请日：2002-11-12

申请人： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

发明人： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC分类号： H04L23/00

CPC分类号： H04L25/06 ,  H04L7/033 ,  H04L25/0266 ,  H04M11/06 ,  H04M19/001

摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

摘要翻译： 可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。 简要描述，DAA提供用于各种国际电话标准的DC终端的可编程装置。 本发明还可以用于在电容隔离屏障上传输和接收信号的装置。 更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。 在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。 此外，大部分功率可能会在外部无源器件（如电阻）中消散。

公开(公告)号：US07289145B2

公开(公告)日：2007-10-30

申请号：US11415000

申请日：2006-05-01

申请人： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

发明人： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

IPC分类号： H04N5/235

CPC分类号： H04N5/3575 ,  H04N5/335 ,  H04N5/361

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路 所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。 处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。