公开(公告)号：US07198990B2

公开(公告)日：2007-04-03

申请号：US11137811

申请日：2005-05-24

申请人： Rajiv V. Joshi ,  Richard Q. Williams

发明人： Rajiv V. Joshi ,  Richard Q. Williams

IPC分类号： H01L21/335

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。 栅极通过栅极电介质耦合到沟道封套。 示例性材料是Si和Si x Ge 1-x x，其中78

公开(公告)号：US07102181B1

公开(公告)日：2006-09-05

申请号：US10907971

申请日：2005-04-22

申请人： Edward J. Nowak ,  Richard Q. Williams

发明人： Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.

公开(公告)号：US06420772B1

公开(公告)日：2002-07-16

申请号：US09417438

申请日：1999-10-13

申请人： Kurt R. Kimmel ,  J. Alex Chediak ,  William T. Motsiff ,  Wilbur D. Pricer ,  Richard Q. Williams

发明人： Kurt R. Kimmel ,  J. Alex Chediak ,  William T. Motsiff ,  Wilbur D. Pricer ,  Richard Q. Williams

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  G11C11/5607 ,  G11C2216/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

摘要翻译： 一种用于可编程电路的方法和结构，其包括具有可改变的磁阻的磁性装置。 磁性装置可以被编程为三个磁场中的一个或多个状态。 传统的VLSI制造步骤用于与低k电介质后端（BEOL）处理的兼容性。

公开(公告)号：US6022770A

公开(公告)日：2000-02-08

申请号：US47155

申请日：1998-03-24

申请人： Terence B. Hook ,  James S. Nakos ,  Richard Q. Williams

发明人： Terence B. Hook ,  James S. Nakos ,  Richard Q. Williams

IPC分类号： H01L21/8247 ,  H01L21/762 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238

CPC分类号： H01L27/105

摘要： Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and increasing potential integration density by using thin film transistors for high voltage switching and isolating the thin film transistors from the substrate by forming the thin film transistors on isolation structures extending between or over elements formed at a surface of a substrate or semiconductor layer. Geometry and doping levels of the thin film transistors is thus made independent of geometry and doping levels of the non-volatile semiconductor memory cells and other field effect transistors operating at lower logic-level voltages. In particular, the thickness of a doped semiconductor layer in which an impurity well may be formed can be determined in a manner to optimize performance of transistors operating at logic level voltages rather than the breakdown voltage which must be withstood by transistors used for controlling write and erase operations of the non-volatile memory cells.

摘要翻译： 集成在非易失性半导体存储器单元中的场效应晶体管的击穿和闭锁需要高于写入和擦除操作的逻辑电平电压，同时通过使用薄膜晶体管来实现高电压，从而限制工艺复杂性和约束并增加潜在的集成密度 通过在形成在衬底或半导体层的表面上的元件之间或之上延伸的隔离结构上形成薄膜晶体管，从而将薄膜晶体管与衬底隔离开来并隔离。 因此，薄膜晶体管的几何和掺杂水平独立于在较低逻辑电平电压下工作的非易失性半导体存储器单元和其它场效应晶体管的几何形状和掺杂水平。 特别地，其中可以形成杂质阱的掺杂半导体层的厚度可以以优化以逻辑电平电压工作的晶体管的性能而不是由用于控制写入的晶体管所必须承受的击穿电压的方式来确定， 擦除非易失性存储单元的操作。