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    Apparatus and method for detecting defective NVRAM cells
    1.
    发明授权
    Apparatus and method for detecting defective NVRAM cells 失效
    用于检测有缺陷的NVRAM单元的装置和方法

    公开(公告)号：US06256755B1

    公开(公告)日：2001-07-03

    申请号：US09174789

    申请日：1998-10-19

    申请人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

    发明人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

    IPC分类号： G11C2900

    CPC分类号： G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

    摘要： An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

    摘要翻译： 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

    NVRAM utilizing high voltage TFT device and method for making the same
    2.
    发明授权
    NVRAM utilizing high voltage TFT device and method for making the same 失效
    采用高压TFT器件的NVRAM及其制造方法

    公开(公告)号：US6022770A

    公开(公告)日：2000-02-08

    申请号：US47155

    申请日：1998-03-24

    申请人： Terence B. Hook ,  James S. Nakos ,  Richard Q. Williams

    发明人： Terence B. Hook ,  James S. Nakos ,  Richard Q. Williams

    IPC分类号： H01L21/8247 ,  H01L21/762 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238

    CPC分类号： H01L27/105

    摘要： Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and increasing potential integration density by using thin film transistors for high voltage switching and isolating the thin film transistors from the substrate by forming the thin film transistors on isolation structures extending between or over elements formed at a surface of a substrate or semiconductor layer. Geometry and doping levels of the thin film transistors is thus made independent of geometry and doping levels of the non-volatile semiconductor memory cells and other field effect transistors operating at lower logic-level voltages. In particular, the thickness of a doped semiconductor layer in which an impurity well may be formed can be determined in a manner to optimize performance of transistors operating at logic level voltages rather than the breakdown voltage which must be withstood by transistors used for controlling write and erase operations of the non-volatile memory cells.

    摘要翻译： 集成在非易失性半导体存储器单元中的场效应晶体管的击穿和闭锁需要高于写入和擦除操作的逻辑电平电压，同时通过使用薄膜晶体管来实现高电压，从而限制工艺复杂性和约束并增加潜在的集成密度 通过在形成在衬底或半导体层的表面上的元件之间或之上延伸的隔离结构上形成薄膜晶体管，从而将薄膜晶体管与衬底隔离开来并隔离。 因此，薄膜晶体管的几何和掺杂水平独立于在较低逻辑电平电压下工作的非易失性半导体存储器单元和其它场效应晶体管的几何形状和掺杂水平。 特别地，其中可以形成杂质阱的掺杂半导体层的厚度可以以优化以逻辑电平电压工作的晶体管的性能而不是由用于控制写入的晶体管所必须承受的击穿电压的方式来确定， 擦除非易失性存储单元的操作。

    Nonvolatile memory cell using microelectromechanical device
    3.
    发明授权
    Nonvolatile memory cell using microelectromechanical device 失效
    使用微机电装置的非易失性存储单元

    公开(公告)号：US6054745A

    公开(公告)日：2000-04-25

    申请号：US225071

    申请日：1999-01-04

    申请人： James S. Nakos ,  Richard Q. Williams

    发明人： James S. Nakos ,  Richard Q. Williams

    IPC分类号： B81B3/00 ,  H01H59/00 ,  H01L27/105 ,  H01L29/72

    CPC分类号： H01L27/105 ,  H01H59/0009

    摘要： A nonvolatile memory cell comprises a conductive cantilever beam having a free end in a first charge state, a first FET having a conductive gate in a second charge state and a pull-in electrode adapted to bring the cantilever beam into electrical contact with the gate to effect a charge state change in the gate. A pull-in electrode input is connected to the electrode, a cantilever input is connected to the cantilever, a column select input is connected to the first FET and a row select input is connected to the first FET. The nonvolatile memory cell is selected by signals applied to the row select input and the column select input. The cell also includes a second FET connected between the cantilever beam and the cantilever input for controlling the passage of signals from the cantilever input to the cantilever beam and a third FET connected between the pull-in electrode and the pull-in electrode input for controlling the passage of signals from the pull-in electrode input to the electrode. The second FET and third FET have gates connected to the row select input. The row select input turns on the second FET and the third FET to allow the passage of signals from the pull-in electrode input to the pull-in electrode and from the cantilever input to the cantilever beam when the nonvolatile memory cell is selected.

    摘要翻译： 非易失性存储单元包括具有处于第一充电状态的自由端的导电悬臂梁，具有第二充电状态的导电栅极的第一FET和适于使悬臂梁与栅极电接触的引入电极 影响门的充电状态变化。 一个引入电极的输入端与电极连接，一个悬臂输入连接到悬臂上，一个列选择输入端连接到第一个FET，一个行选择输入端连接到第一个FET。 通过施加到行选择输入和列选择输入的信号来选择非易失性存储单元。 电池还包括连接在悬臂梁和悬臂输入端之间的第二FET，用于控制从悬臂输入到悬臂梁的信号通过;以及连接在引入电极和引入电极输入端之间的第三FET，用于控制 信号从拉入电极输入到电极的通过。 第二FET和第三FET具有连接到行选择输入的栅极。 当选择非易失性存储单元时，行选择输入打开第二FET和第三FET以允许从拉入电极输入到拉入电极的信号以及从悬臂输入到悬臂梁的信号。

    Field effect transistor structure and method of forming same
    4.
    发明授权
    Field effect transistor structure and method of forming same 有权
    场效应晶体管结构及其形成方法

    公开(公告)号：US08835261B2

    公开(公告)日：2014-09-16

    申请号：US13046902

    申请日：2011-03-14

    申请人： Edward J. Nowak ,  Richard Q. Williams

    发明人： Edward J. Nowak ,  Richard Q. Williams

    IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/31

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

    摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.

    摘要翻译： 本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

    Doped single crystal silicon silicided eFuse
    7.
    发明授权
    Doped single crystal silicon silicided eFuse 有权
    掺杂单晶硅硅片eFuse

    公开(公告)号：US07572724B2

    公开(公告)日：2009-08-11

    申请号：US12043226

    申请日：2008-03-06

    申请人： Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti ,  Richard Q. Williams

    发明人： Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.

    摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。 将单晶硅层图案化成条带。 在构图之前或之后，单晶硅层掺杂有一种或多种杂质。 至少单晶硅层的上部然后被硅化以形成硅化带。 在一个实施例中，整个单晶硅带被硅化以产生硅化物条。 在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。 在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。 通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。 上覆的硅化物材料允许熔丝作为未编程状态的导体。 然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

    CURVED FINFETS
    9.
    发明申请
    CURVED FINFETS 有权
    弯曲的熔体

    公开(公告)号：US20080164535A1

    公开(公告)日：2008-07-10

    申请号：US11621228

    申请日：2007-01-09

    申请人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    发明人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7843

    摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.

    摘要翻译： 一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。 然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。 接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。 翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的 移动，中央部分不能自由移动。 在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。 因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

    Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
    10.
    发明授权
    Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
    基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化

    公开(公告)号：US07337420B2

    公开(公告)日：2008-02-26

    申请号：US11193711

    申请日：2005-07-29

    申请人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

    发明人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

    摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

    摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。