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公开(公告)号：US10818664B2
公开(公告)日：2020-10-27
申请号：US16512306
申请日：2019-07-15
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , H01L49/02 , G11C11/4074 , G11C7/02 , G11C11/404
Abstract: A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
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公开(公告)号：US20200212042A1
公开(公告)日：2020-07-02
申请号：US16812384
申请日：2020-03-09
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chieh-Te Chen
IPC: H01L27/108 , H01L21/02 , H01L49/02 , H01L21/311
Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.
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公开(公告)号：US20200176453A1
公开(公告)日：2020-06-04
申请号：US16779670
申请日：2020-02-03
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L27/108
Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
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公开(公告)号：US20200083317A1
公开(公告)日：2020-03-12
申请号：US16154680
申请日：2018-10-08
Inventor： Kai-Lou Huang , Fu-Che Lee , Feng-Yi Chang , Chieh-Te Chen , Meng-Chia Tsai
IPC: H01L49/02 , H01L23/532
Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
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公开(公告)号：US10559651B2
公开(公告)日：2020-02-11
申请号：US16114217
申请日：2018-08-28
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L21/3213 , H01L27/08 , H01L49/02 , H01L27/108
Abstract: The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.
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Patent Agency Ranking
公开(公告)号：US10418367B2
公开(公告)日：2019-09-17
申请号：US16029638
申请日：2018-07-08
Inventor： Yi-Ching Chang , Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L21/768 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
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公开(公告)号：US10373957B2
公开(公告)日：2019-08-06
申请号：US15856084
申请日：2017-12-28
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chieh-Te Chen
IPC: H01L27/108 , H01L21/311 , H01L21/02 , H01L49/02
Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
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公开(公告)号：US20190189621A1
公开(公告)日：2019-06-20
申请号：US16273057
申请日：2019-02-11
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , H01L21/768
CPC classification number: H01L27/10894 , H01L21/7682 , H01L27/10808 , H01L27/10823 , H01L27/10852 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897
Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.
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公开(公告)号：US20190109138A1
公开(公告)日：2019-04-11
申请号：US16211239
申请日：2018-12-06
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , H01L21/768
CPC classification number: H01L27/10885 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L21/76897 , H01L27/10814 , H01L27/10823 , H01L27/10888 , H01L27/10894 , H01L27/10897
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
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公开(公告)号：US20190100430A1
公开(公告)日：2019-04-04
申请号：US15801308
申请日：2017-11-01
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
Abstract: A method of forming a semiconductor device includes following steps. First of all, plural first openings and plural second openings are sequentially formed on a material layer disposed on a substrate, with the second openings across the first openings to form plural overlapped regions. Then, plural patterns arranged in an array arrangement are formed, with each pattern overlapped each overlapped region, respectively. After that, transferring the first openings, the second openings and the patterns to the material layer, to from plural material patterns in an array arrangement. In another embodiment of the present invention, the first openings and the second openings may be replaced by plural first patterns and plural second patterns, while the patterns are replaced by plural openings.
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