公开(公告)号：US5267210A

公开(公告)日：1993-11-30

申请号：US25894

申请日：1993-03-03

申请人： David C. McClure ,  Mark A. Lysinger

发明人： David C. McClure ,  Mark A. Lysinger

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C7/20 ,  G11C11/412 ,  G11C11/40

CPC分类号： G11C11/412 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20

摘要： A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

摘要翻译： 具有多个I / O的静态随机存取存储器包括存储器单元（42）的存储器阵列（10），所述存储器单元（42）具有作为相关I / O的函数可选择地清零的列。 这些列以成对（34）排列，成对（34）中的每个列与相同的I / O相关联。 在线路（28）上输入清除信号并由驱动器（30）驱动。 清除信号仅与与选择的I / O相关联的对（34）相关联。 与未选择的I / O相关联的其余存储单元列不会被清除。

公开(公告)号：US5257226A

公开(公告)日：1993-10-26

申请号：US809733

申请日：1991-12-17

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/10 ,  G11C

CPC分类号： G11C7/1048

摘要： An integrated circuit, such as a memory, having an internal data bus and circuitry for precharging the same, with each data conductor in the said data bus associated with a dummy data conductor, which is driven to a complementary logic state from that of its associated data conductor. During precharge and equilibration at the beginning of a cycle, initiated by an address transition detection or by a clock signal, each data conductor is connected to its dummy data conductor so that the data conductor is precharged to a midlevel by way of charge sharing. Also during precharge and equilibration, the data driver is placed in a high impedance state by the sense amplifier output nodes both going to the same logic level. This midlevel precharge allows for faster switching, and reduced instantaneous current, than obtained for rail-to-rail switching. Self-biasing circuits are connected to each of the data conductors and dummy data conductors, to prevent floating conditions during long precharge and equilibration periods. The output stage receiving the data conductor is preferably disabled during precharge and equilibration, so that the data conductor can be precharged near the trip level of the output stage, without risking output stage oscillations. A termination is also provided for the dummy data conductor, matching the load presented by the output stage to the data conductor, so that the data conductor and its dummy data conductor are at complementary states even during transient conditions.

摘要翻译： 诸如存储器的集成电路具有内部数据总线和用于对其进行预充电的电路，与与虚拟数据导体相关联的所述数据总线中的每个数据导体被驱动到与其相关联的逻辑状态的互补逻辑状态 数据线。 在循环开始期间，通过地址转换检测或时钟信号启动的预充电和平衡期间，每个数据导体连接到其虚拟数据导体，使得数据导体通过电荷共享被预充电到中间级。 此外，在预充电和平衡期间，数据驱动器由感测放大器输出节点置于高阻抗状态，两者都达到相同的逻辑电平。 该中级预充电允许比轨至轨切换获得的更快的开关和减小的瞬时电流。 自偏置电路连接到每个数据导体和虚拟数据导体，以防止在长预充电和平衡周期期间的浮动状态。 接收数据导体的输出级优选在预充电和平衡期间被禁用，使得数据导体可以在输出级的跳闸电平附近被预充电，而不会产生输出级振荡。 还为虚拟数据导体提供终端，使输出级呈现的负载与数据导体相匹配，使得数据导体及其虚拟数据导体即使在瞬态条件下也处于互补状态。

公开(公告)号：US5124584A

公开(公告)日：1992-06-23

申请号：US601287

申请日：1990-10-22

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/41 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  G11C11/409 ,  G11C11/413 ,  H03K5/1252

CPC分类号： G11C8/18 ,  G11C8/06

摘要： An input buffer circuit having a latching function controlled by a transition detection circuit is disclosed. The input stage of the input buffer is connected to a delay stage, and to a transition detection circuit. The output of the delay stage is connected to a pass gate, which is controlled by the output of the transition detection circuit; a latch is connected to the other side of the pass gate. The transition detection circuit produces a pulse responsive to a transition, and the pass gate is turned off during the length of the pulse, with the latch maintaining and presenting the state of the input prior to the transition. After the pulse is complete, the new value of the input signal is latched and presented to the circuit. Since the pass gate is turned off during the transition detection pulse, a short and spurious transition at the input terminal is isolated from the latch by the pass gate (with the transition detection pulse lengthened), and does not appear at the output of the input buffer circuit.

公开(公告)号：US4935719A

公开(公告)日：1990-06-19

申请号：US332288

申请日：1989-03-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F5/14 ,  G06F7/02 ,  G06F7/04 ,  G06F7/50 ,  G06F13/38 ,  G11C7/00

CPC分类号： G06F7/026

摘要： Two sets of binary data of N bits in length are compared by first forming the exclusive OR function of each of the corresponding bits of the two data sets. The output of each of the exclusive OR gates controls two sets of transmission gates in each of N comparator circuits which are combined in series. If an individual pair of bits are the same, then the comparator circuit transfers the data from its compare input to its compare output, and if the individual bits are different, the respective compare circuit transfers the data from the respective bit on one of the buses to the compare output of the circuit. The compare input of the first compare circuit is connected to ground and the compare input of the rest of the comparator circuits is connected to the compare output of the previous circuit and the compare output of the Nth compare circuit forms a signal indicative of whether the data on the first bus is greater than the data on the second bus.

公开(公告)号：US08827165B2

公开(公告)日：2014-09-09

申请号：US13039832

申请日：2011-03-03

申请人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

发明人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

IPC分类号： G06K19/06 ,  G11C16/22 ,  G11C16/20 ,  G11C17/16

CPC分类号： G11C16/20 ,  G11C16/22 ,  G11C17/16

摘要： An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

摘要翻译： 集成电路包括输出焊盘，报警输出焊盘和测试模式输出焊盘。 第一个多位寄存器是可编程的，用于存储可编程数据，例如识别已经制造了集成电路的客户的数据。 可编程第二个多位寄存器来存储客户指定的阈值数据。 第一电路将第一和第二多位寄存器选择性地耦合到输出焊盘。 第一电路可操作地响应于集成电路被放置在测试模式中，以执行存储在第一多位寄存器中的客户识别数据或存储在第二多位寄存器中的客户指定的阈值数据的并行 - 串行转换， 位寄存器，并通过输出板驱动转换后的数据输出。 集成电路还包括可响应于客户指定的阈值数据操作的篡改检测电路，以产生篡改报警信号。 第二电路根据集成电路是否处于测试模式，选择性地将篡改报警信号耦合到报警输出焊盘和测试模式输出焊盘。 更具体地，当集成电路不处于测试模式时，第二电路用于驱动具有篡改报警信号的报警输出板，并且当集成电路处于测试模式时驱动具有篡改报警信号的测试模式输出板 报警输出板驱动到已知状态）。

公开(公告)号：US07623405B2

公开(公告)日：2009-11-24

申请号：US12030463

申请日：2008-02-13

申请人： Mark A. Lysinger ,  David C. McClure ,  François Jacquet

发明人： Mark A. Lysinger ,  David C. McClure ,  François Jacquet

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C11/412 ,  G11C11/413

摘要： A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

摘要翻译： 电路包括具有高电压供应节点和低电压供应节点的存储单元。 功率复用电路被包括以根据小区的当前操作模式来选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 阵列可以包括包括许多块或部分在内的整个存储器件中的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。

公开(公告)号：US20080191917A1

公开(公告)日：2008-08-14

申请号：US12020861

申请日：2008-01-28

申请人： David C. McClure ,  Sooping Saw

发明人： David C. McClure ,  Sooping Saw

IPC分类号： H03M1/66

CPC分类号： G01K3/005 ,  G01K7/015

摘要： A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.

摘要翻译： 数模转换器响应于数字信号，选择性地抽头电阻串以产生模拟输出，并选择性地分流串中的电阻器以对模拟输出进行电压移位。 如果存在两个电源电压组，则提供两个串。 选择输出的相互选择来选择模拟输出的源。 集成电路温度传感器使用转换器并且包括确定暴露于相对低或高温度之一的感测电路。 在低温暴露下选择双极晶体管的基极 - 发射极两端的测量电压，并与太冷的温度条件下的第一参考值相比较。 或者，在高温暴露中选择基极 - 发射极两端的测量的增量电压，并与过热温度条件下的第二参考电压进行比较。 通过比较，进行温度曝光检测。

公开(公告)号：US06816400B2

公开(公告)日：2004-11-09

申请号：US10436801

申请日：2003-05-12

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C1122

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5004

摘要： A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

摘要翻译： 公开了一种用于测试具有铁电存储器单元阵列的铁电存储器件的存储单元的测试电路和方法。 测试电路耦合到列线，用于选择性地感测列线上出现的电压电平，并向铁电存储器件外部提供表示感测电压电平的电信号。 以这种方式，可以确定表现出降低性能的铁电存储器单元。

公开(公告)号：US06787938B1

公开(公告)日：2004-09-07

申请号：US09626550

申请日：2000-07-27

申请人： David C. McClure ,  Tom Youssef

发明人： David C. McClure ,  Tom Youssef

IPC分类号： G01R2316

CPC分类号： G11C5/141 ,  Y10T307/615 ,  Y10T307/625 ,  Y10T307/826

摘要： An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

摘要翻译： 一种用于提供从主电源到次电源的切换以防止易失性元件丢失存储的数据的集成电路和方法。 集成电路包括强制电源切换电路，用于检测主电源的电源电平低于预定阈值电平。 集成电路中的切换电路基于强制电源切换电路检测到从主电源接收的电源电平下降到低于预定阈值水平的情况下开始切换操作。 强制电源切换电路的检测可能发生在比预定的负变化率更快地转变的信号电平上。 集成电路可以并入具有诸如存储器或时钟之类的易失性元件的任何系统中。

公开(公告)号：US06781916B2

公开(公告)日：2004-08-24

申请号：US10442844

申请日：2003-05-20

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C700

CPC分类号： G11C29/027 ,  G11C11/22 ,  G11C11/41 ,  G11C14/00 ,  G11C29/50 ,  G11C2029/5004

摘要： A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.

摘要翻译： 一种具有第一和第二存储器部分的存储器件，所述第一和第二存储器部分耦合到位线。 第二存储器部分可以包括至少一个熔丝。 第一存储器部分包括易失性存储器，并且第二存储器部分包括非易失性存储器。 易失性存储器可以是静态或动态随机存取存储器。 存储器件还可以包括连接到至少一个保险丝以提供预激光器测试的控制电路。