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113 条记录 (耗时 0.047 秒)

    Semiconductor device
    71.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060285576A1

    公开(公告)日：2006-12-21

    申请号：US11452317

    申请日：2006-06-14

    申请人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

    发明人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

    IPC分类号： G01K7/00 ,  H05B1/02

    CPC分类号： G01K7/01

    摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

    摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

    Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage
    73.
    发明申请
    Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage 失效
    内部电源电压发生电路，可以抑制外部电源电压下限附近的内部电源电压的降低

    公开(公告)号：US20050280465A1

    公开(公告)日：2005-12-22

    申请号：US11210845

    申请日：2005-08-25

    申请人： Fukashi Morishita

    发明人： Fukashi Morishita

    IPC分类号： H02J1/00 ,  G05F1/46 ,  G05F3/24 ,  G11C11/407 ,  H05B37/02

    CPC分类号： G05F1/465

    摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

    摘要翻译： 内部电源电压产生电路包括主放大器，该主放大器根据来自基准电压产生电路的参考电压和内部电源电压之间的差，从外部电源节点向内部电源线提供电流 内部电源线。 根据外部电源电压和参考电压之间的差异，通过电平调整电路调整主放大器的电流供给量。 内部电源电压产生电路可以抑制差分电源电压的下限区域附近的内部电源电压的降低。

    Semiconductor memory device with circuit executing burn-in testing
    77.
    发明授权
    Semiconductor memory device with circuit executing burn-in testing 失效
    具有执行老化测试的电路的半导体存储器件

    公开(公告)号：US06704231B1

    公开(公告)日：2004-03-09

    申请号：US10397211

    申请日：2003-03-27

    申请人： Fukashi Morishita ,  Mitsuya Kinoshita

    发明人： Fukashi Morishita ,  Mitsuya Kinoshita

    IPC分类号： G11C700

    CPC分类号： G11C29/12005 ,  G11C29/12 ,  G11C2029/1204

    摘要： A semiconductor memory device includes an isolation unit isolating a bit line in a first region including a memory cell formed of a thick film transistor and a second region including a sense amplifier formed of a thin film transistor. Voltage supply lines are provided corresponding to respective regions. In a test mode, the isolation unit isolates the two regions. A voltage for testing is supplied from the voltage supply line. Thus, a voltage for testing corresponding to a thick film transistor and a thin film transistor can be supplied to allow efficient execution of a burn-in test.

    摘要翻译： 半导体存储器件包括隔离单元，隔离包括由厚膜晶体管形成的存储单元的第一区域和包括由薄膜晶体管形成的读出放大器的第二区域的位线。 对应于各个区域提供电压供应线。 在测试模式下，隔离单元隔离两个区域。 用于测试的电压从电源线供应。 因此，可以提供与厚膜晶体管和薄膜晶体管相对应的用于测试的电压，以有效地执行老化测试。

    Semiconductor memory device including internal power circuit having tuning function
    78.
    发明授权
    Semiconductor memory device including internal power circuit having tuning function 失效
    半导体存储器件包括具有调谐功能的内部电源电路

    公开(公告)号：US06665217B2

    公开(公告)日：2003-12-16

    申请号：US10120575

    申请日：2002-04-12

    申请人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

    发明人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

    IPC分类号： G11C700

    CPC分类号： G11C5/025 ,  G11C5/147

    摘要： A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

    摘要翻译： 调谐控制电路包括响应于来自外部的程序输入而从导通状态转换到中断状态的熔丝器件，以及根据保险丝器件的状态来驱动调谐控制信号的信号电平的信号驱动电路。 参考电压产生电路根据根据本发明的半导体存储器件的存储器阵列电压的参考值产生与根据调谐控制信号精细调节的电阻值相对应的参考电压。

    Semiconductor integrated circuit device having circuit generating reference voltage
    80.
    发明授权
    Semiconductor integrated circuit device having circuit generating reference voltage 失效
    具有电路产生参考电压的半导体集成电路器件

    公开(公告)号：US06429729B2

    公开(公告)日：2002-08-06

    申请号：US09758273

    申请日：2001-01-12

    申请人： Mako Kobayashi ,  Fukashi Morishita ,  Mihoko Akiyama ,  Yasuhiko Taito ,  Akira Yamazaki ,  Nobuyuki Fujii

    发明人： Mako Kobayashi ,  Fukashi Morishita ,  Mihoko Akiyama ,  Yasuhiko Taito ,  Akira Yamazaki ,  Nobuyuki Fujii

    IPC分类号： G05F110

    CPC分类号： G05F1/465

    摘要： A semiconductor integrated circuit device includes a reference voltage generating circuit that can be tuned without a circuit replacement when a process condition is varied. The reference voltage generating circuit is constituted such that two different circuit configurations having different temperature properties are switched by a first switch. In each of the circuit configurations, a switch control circuit in which tuning can be performed by switching a second switch generates a control signal based on a test mode and supplies the signal to the first switch for tuning. Thereafter, a fuse in the switch control circuit is blown off to generate a control signal, and reference voltage Vref is output.

    摘要翻译： 一种半导体集成电路器件，包括一个参考电压产生电路，当一个工艺条件变化时，该参考电压产生电路可被调谐而没有电路更换。 参考电压产生电路被构造成使得通过第一开关切换具有不同温度特性的两个不同的电路配置。 在每个电路配置中，可以通过切换第二开关来执行调谐的开关控制电路基于测试模式产生控制信号，并将该信号提供给第一开关进行调谐。 此后，开关控制电路中的保险丝被断开以产生控制信号，并输出参考电压Vref。