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39 条记录 (耗时 0.018 秒)

    Clock generating circuit
    1.
    发明授权
    Clock generating circuit 失效
    时钟发生电路

    公开(公告)号：US06781431B2

    公开(公告)日：2004-08-24

    申请号：US10349033

    申请日：2003-01-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    IPC分类号： G06F104

    CPC分类号： H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

    摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

    摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

    Semiconductor memory device with internal power supply potential generation circuit
    2.
    发明授权
    Semiconductor memory device with internal power supply potential generation circuit 失效
    具有内部电源电位生成电路的半导体存储器件

    公开(公告)号：US06424579B1

    公开(公告)日：2002-07-23

    申请号：US09827897

    申请日：2001-04-09

    申请人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    发明人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    IPC分类号： G11C700

    CPC分类号： G11C5/147

    摘要： In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.

    摘要翻译： 在eDRAM中，提供了一个VDC，其降低转换外部电源电位以产生用于读出放大器频带的内部电源电位;以及VDC，其降低转换外部电源电位以产生内部电源电位 用于列解码器。 通过仅在对应于读出放大器的放大操作的时间段期间增加VDC的通过电流来提高VDC的响应。 因此，电流消耗小于将VDC的通电电流设定为高恒定电平的常规情况。