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    Inductive filters and methods of fabrication thereof
    71.
    发明授权
    Inductive filters and methods of fabrication thereof 有权
    电感式滤波器及其制造方法

    公开(公告)号：US07111271B2

    公开(公告)日：2006-09-19

    申请号：US10281752

    申请日：2002-10-28

    申请人： Yuan-Liang Li ,  David G. Figueroa

    发明人： Yuan-Liang Li ,  David G. Figueroa

    IPC分类号： G06F17/50 ,  H03K17/693

    CPC分类号： H01F17/0033 ,  H01F41/041 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15312 ,  H05K1/115 ,  H05K1/165 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1006 ,  H05K2203/0723 ,  H01L2224/0401

    摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.

    摘要翻译： 一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。 该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。 在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。 在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。 铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。 在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。 制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。 在一些实施例中，板包括嵌入的铁磁材料图案。 电介质板的孔和顶表面和底表面具有导电材料。 选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

    System to control effective series resistance of decoupling capacitor
    72.
    发明申请
    System to control effective series resistance of decoupling capacitor 有权
    系统来控制去耦电容的有效串联电阻

    公开(公告)号：US20060091564A1

    公开(公告)日：2006-05-04

    申请号：US10976716

    申请日：2004-10-29

    申请人： Dong Zhong ,  David Figueroa ,  Yuan-Liang Li ,  Michael Desmith

    发明人： Dong Zhong ,  David Figueroa ,  Yuan-Liang Li ,  Michael Desmith

    IPC分类号： H01L23/52 ,  H01L23/48

    CPC分类号： H01L23/50 ,  H01L2224/16225 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106

    摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.

    摘要翻译： 根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。 集成电路封装可以包括多个导电触点和去耦电容器。 去耦电容器可以包括耦合到多个导电触点中的第一个的正极端子接触焊盘，正极端子接触焊盘包括第一基本上不导电的区域，以及耦合到多个导电触点中的第二个的负极端子接触焊盘 的导电触点，负极接触焊盘包括第二基本上不导电的区域。

    Low impedance, high-power socket and method of using
    73.
    发明授权
    Low impedance, high-power socket and method of using 失效
    低阻抗，大功率插座和使用方法

    公开(公告)号：US06964584B2

    公开(公告)日：2005-11-15

    申请号：US10032377

    申请日：2001-12-21

    申请人： Dong Zhong ,  Yuan-Liang Li ,  David G. Figueroa ,  Jiangqi He

    发明人： Dong Zhong ,  Yuan-Liang Li ,  David G. Figueroa ,  Jiangqi He

    IPC分类号： H01R13/6466 ,  H01R13/6473 ,  H01R13/66

    CPC分类号： H01R13/6625 ,  H01R13/6466 ,  H01R13/6473

    摘要： The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.

    摘要翻译： 本发明涉及一种用于微电子器件的电源插座，其在一个实施例中使用低电阻功率和接地端子配置。 在另一个实施例中，低电阻功率和接地端子配置结合在电源插座上，并具有用于降低电感的垂直取向的交叉指状电容器。 通过该组合，在微电子器件的操作期间实现显着降低的阻抗。 电容器可以包括相对于插座面的主平面垂直定向的板，并且电容器可以位于电源和接地触点之间，两个电源触点之间或两个接地触点之间。

    Hybrid capacitor, circuit, and system
    74.
    发明授权
    Hybrid capacitor, circuit, and system 失效
    混合电容，电路和系统

    公开(公告)号：US06920051B2

    公开(公告)日：2005-07-19

    申请号：US10155628

    申请日：2002-05-24

    申请人： David G. Figueroa ,  Yuan-Liang Li ,  Huong T. Do

    发明人： David G. Figueroa ,  Yuan-Liang Li ,  Huong T. Do

    IPC分类号： H01L23/64 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18

    CPC分类号： H01L23/642 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/162 ,  Y10T29/435 ,  H01L2924/00

    摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.

    摘要翻译： 与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。 混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。 平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。 片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。 每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。 内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。 分立电容器电连接到从导电层到封装表面的触点。 在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

    Electrical-optical package with capacitor DC shunts and associated methods
    78.
    发明授权
    Electrical-optical package with capacitor DC shunts and associated methods 有权
    带电容器的电光封装直流分流器及相关方法

    公开(公告)号：US06624444B1

    公开(公告)日：2003-09-23

    申请号：US10109314

    申请日：2002-03-28

    申请人： Yuan-Liang Li

    发明人： Yuan-Liang Li

    IPC分类号： H01L2904

    CPC分类号： G02B6/43 ,  G02B6/4232 ,  H01L31/12 ,  H01L2224/16225

    摘要： An optical-electrical (OE) package includes a substrate electrically coupled to a motherboard via one or more capacitor DC shunts (CDCSs). In one embodiment, the substrate includes an IC chip electrically coupled to a first set of contact-receiving members on an upper surface of the substrate. The substrate also includes a light-emitting package and a photodetector package electrically coupled to respective second and third sets of contact-receiving members on the substrate lower surface. The substrate has internal wiring that electrically interconnects the IC chip, the light-emitting package and the photodetector array. The light-emitting package and the photodetector array are optically coupled to respective first and second waveguide arrays formed in or on the motherboard. The CDCSs mitigate noise generated by the IC chip by serving as a local current source.

    摘要翻译： 光电（OE）封装包括经由一个或多个电容器DC分路（CDCS）电耦合到母板的基板。 在一个实施例中，衬底包括电连接到衬底的上表面上的第一组接触件的IC芯片。 衬底还包括发光封装和光电检测器封装，电耦合到衬底下表面上相应的第二组和第三组接触件。 衬底具有将IC芯片，发光封装和光电检测器阵列电互连的内部布线。 发光封装和光电检测器阵列光学耦合到形成在母板中或母板上的相应的第一和第二波导阵列。 CDCS通过作为本地电流源来减轻由IC芯片产生的噪声。

    Electronic assembly providing shunting of electrical current
    80.
    发明授权
    Electronic assembly providing shunting of electrical current 失效

    公开(公告)号：US06476477B2

    公开(公告)日：2002-11-05

    申请号：US09729813

    申请日：2000-12-04

    申请人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

    发明人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

    IPC分类号： H01L2352

    CPC分类号： H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.