System and method for protecting communication between a central office and a remote premises
    71.
    发明授权
    System and method for protecting communication between a central office and a remote premises 有权
    用于保护中心局和远程办公室之间的通信的系统和方法

    公开(公告)号:US07457234B1

    公开(公告)日:2008-11-25

    申请号:US10790158

    申请日:2004-03-01

    IPC分类号: H04J1/16 H04J3/14

    CPC分类号: H04Q1/028

    摘要: A data communication system for communicating between a central office and a remote premises comprises a first transceiver, a second transceiver, and control logic. The first transceiver is coupled to a first communication connection extending from the central office to the remote premises and is configured to communicate with a central office transceiver. The second transceiver is coupled to a second communication connection extending from the central office to the remote premises. The control logic resides at the remote premises and is configured to detect an error condition associated with communication between the first transceiver and the transceiver located at the central office. The control logic is configured to transmit, in response to a detection of the error condition, a switch notification to the central office via the second transceiver and the second communication connection, wherein at least one component at the central office is configured to route data over the second communication connection in response to the switch notification.

    摘要翻译: 用于在中心局和远程场所之间进行通信的数据通信系统包括第一收发器,第二收发器和控制逻辑。 第一收发器耦合到从中心局延伸到远程房屋的第一通信连接,并且被配置为与中心局收发器通信。 第二收发器耦合到从中心局延伸到远程房屋的第二通信连接。 控制逻辑驻留在远程房屋处,并被配置为检测与第一收发器和位于中心局的收发器之间的通信相关联的错误状况。 控制逻辑被配置为响应于错误状况的检测而发送经由第二收发器和第二通信连接到中心局的切换通知,其中中心局的至少一个组件被配置为将数据路由 所述第二通信连接响应于所述切换通知。

    Full duplex voice path capture buffer with time stamp
    72.
    发明授权
    Full duplex voice path capture buffer with time stamp 有权
    全双工语音路径捕获缓冲区带时间戳

    公开(公告)号:US07366161B2

    公开(公告)日:2008-04-29

    申请号:US10337101

    申请日:2003-01-06

    摘要: For diagnostic and trouble-shooting purposes, an audio/voice signal capture mechanism is adapted to be interfaced with a time division multiplexed (TDM) transport path-cascaded echo canceler and compression arrangement for an integrated access device (IAD). The audio/voice signal capture mechanism captures a ‘snapshot’ of the audio/voice signals by storing a prescribed number of seconds of audio/voice path signals transmitted in both directions through the IAD, and time stamping the captured audio/voice signals and associated signaling events of interest. In this way, the invention operates as a ‘virtual’ oscilloscope, as it is able to capture pertinent data for any voice call problem along with an associated time stamp event log.

    摘要翻译: 为了诊断和故障排除目的,音频/语音信号捕获机制适于与用于集成接入设备(IAD)的时分多路复用(TDM)传输路径级联回波消除器和压缩布置接口。 音频/语音信号捕获机构通过存储通过IAD在两个方向上发送的规定数量的音频/语音路径信号来捕获音频/语音信号的“快照”,并且对所捕获的音频/语音信号进行时间戳 信号感兴趣事件。 以这种方式,本发明用作“虚拟”示波器,因为它能够捕获任何语音呼叫问题的相关数据以及关联的时间戳事件日志。

    Modular system for connecting multiple customer premises voice and data communications devices to a T1 data line
    73.
    发明授权
    Modular system for connecting multiple customer premises voice and data communications devices to a T1 data line 有权
    用于将多个客户端语音和数据通信设备连接到T1数据线的模块化系统

    公开(公告)号:US07185115B2

    公开(公告)日:2007-02-27

    申请号:US09834988

    申请日:2001-04-13

    IPC分类号: G06F15/16

    CPC分类号: H04Q11/0471 H02J9/061

    摘要: An integrated system concurrently connects voice and data communications devices used by small and medium sized businesses to a network T1 data line terminating at the customer premises. A system chassis includes multiple slots and backplane connectors for removably receiving a bank controller unit (BCU), power service unit (PSU), and one or more different types of smart and dumb voice and data access modules that provide the functional interface to the customer premises equipment. The BCU controls the operation of the system, which can be configured by the customer through an external terminal interface.

    摘要翻译: 集成系统将中小型企业使用的语音和数据通信设备同时连接到终端于客户驻地的网络T1数据线。 系统机箱包括多个插槽和背板连接器,用于可拆卸地接收银行控制器单元(BCU),电力服务单元(PSU)以及向客户提供功能接口的一个或多个不同类型的智能和哑话音和数据访问模块 处所设备。 BCU控制系统的操作,可由客户通过外部终端接口进行配置。

    Daughtercard-based system software and hardware functionality-defining mechanism
    74.
    发明授权
    Daughtercard-based system software and hardware functionality-defining mechanism 有权
    基于子卡的系统软件和硬件功能定义机制

    公开(公告)号:US07146445B2

    公开(公告)日:2006-12-05

    申请号:US10763784

    申请日:2004-01-23

    IPC分类号: G06F13/00 G06F13/20

    CPC分类号: G06F13/4081

    摘要: A test apparatus for telecommunication equipment includes motherboard that executes a resident operation control mechanism, so that the test apparatus exhibits default hardware functionality. However, if a daughtercard has been plugged into the motherboard, the motherboard ignores the default firmware and executes whatever replacement operation control software is provided on the daughtercard—causing the test apparatus to acquire a hardware functionality exclusive of the motherboard default.

    摘要翻译: 用于电信设备的测试设备包括执行驻留操作控制机构的主板,使得测试设备呈现出默认的硬件功能。 然而,如果子卡已插入主板,则主板将忽略默认固件,并执行子卡上提供的任何替换操作控制软件,导致测试设备获取独占于主板默认值的硬件功能。

    Mechanism for providing octet alignment in serial ATM data stream

    公开(公告)号:US07103049B2

    公开(公告)日:2006-09-05

    申请号:US10040153

    申请日:2002-01-02

    IPC分类号: H04L12/56

    摘要: A byte boundary information recovery mechanism locates the first bits of respective bytes of an asynchronous transfer mode (ATM)-based serial data stream, used by a frame synchronization mechanism to delineate respective cells of the ATM stream, and thereby enables transceiver equipment to successfully receive and parse ATM traffic. The invention employs a counter offset-based scheme that generates an output signal in potential alignment with the (first bit) boundary of a byte of the data stream, in response to the contents of a counter reaching a prescribed count value. It then iteratively shifts, as necessary, the bit time at which the output signal is produced relative to the counting operation of the counter, until the output signal is aligned with the boundary of a byte of the data stream.

    Apparatus and method for interfacing connectors to network components
    76.
    发明授权
    Apparatus and method for interfacing connectors to network components 有权
    将连接器连接到网络组件的装置和方法

    公开(公告)号:US07097493B1

    公开(公告)日:2006-08-29

    申请号:US11035837

    申请日:2005-01-14

    申请人: Marc L. Roth

    发明人: Marc L. Roth

    IPC分类号: H01R11/20

    摘要: The interface apparatus has a connector-receiving unit for receiving a connector that is electrically connected via a conductor to a first device. The connector has a receiving opening corresponding to the conductor. The apparatus further has a port for receiving a cable terminator electrically connected to a second device that is configured to communicate with the network component. Furthermore, the apparatus has a component electrically connected to the port that has a conductive probe movably positioned with respect to the receiving opening corresponding to the conductor of the connector. The component has an actuation component that moves the conductive probe into the receiving opening of the connector when actuated thereby establishing a conductive path between the first device and the second device.

    摘要翻译: 接口装置具有用于接收经由导体电连接到第一装置的连接器的连接器接收单元。 连接器具有对应于导体的接收开口。 该装置还具有用于接收电连接到被配置为与网络部件通信的第二设备的电缆终端器的端口。 此外,该装置具有电连接到端口的部件,该部件具有相对于对应于连接器的导体的接收开口可移动地定位的导电探针。 该部件具有致动部件,该致动部件在致动时将导电探针移动到连接器的接收开口中,从而在第一装置和第二装置之间建立导电路径。

    Mechanism for on-the-fly handling of unaligned memory accesses
    77.
    发明授权
    Mechanism for on-the-fly handling of unaligned memory accesses 有权
    不对齐内存访问的即时处理机制

    公开(公告)号:US07076631B2

    公开(公告)日:2006-07-11

    申请号:US10412854

    申请日:2003-04-14

    IPC分类号: G06F12/00

    摘要: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

    摘要翻译: 通过地址异常处理机制解决了对存储器的不对齐访问,该机制解码异常触发指令,并以逐个字节的方式读取或写入与寻址方案不一致的存储器的寻址部分, 可以执行对存储器的访问,从而引起不对齐的存储器访问异常。 处理程序参照异常堆栈帧模拟指令的执行,保存未对齐地址异常时所有寄存器的内容。 这允许处理程序可控地定义在处理器执行一般异常向量期间恢复为寄存器的值。 在处理异常之后,程序执行转换到直接跟随引发异常指令的下一条指令。

    Binary decision tree-based arbitrator for packetized communications
    78.
    发明授权
    Binary decision tree-based arbitrator for packetized communications 有权
    用于分组通信的二进制决策树仲裁器

    公开(公告)号:US06996071B2

    公开(公告)日:2006-02-07

    申请号:US09845638

    申请日:2001-04-30

    IPC分类号: H04L12/28

    摘要: A binary decision tree-based arbitration scheme executable by a control processor of a time division multiplex (TDM)-based communication system is operative to select the next packet to be transmitted from a plurality of virtual circuits, any number of which may have one or more packets awaiting transmission over a serialized digital communication link. The transmission priority scheme contains N+1 sets of nodes containing 2N+1−1 nodes. A respective ith set of nodes comprises 2i−1 nodes, wherein i is greater than or equal to 1, and less than or equal to N+1. The nodes of a given set are connected to those of an adjacent set by binary-split branches. For each of the 2N leaf nodes of the decision tree, information is stored representative of the transmission priority of a packet awaiting transmission from its associated communication port. In addition, associated with each node branching to respective pairs of downstream nodes (toward the virtual circuit ports) is a ‘pointer’ code that points to whichever one of its two branched nodes is associated with a higher packet transmission priority. As one traverses the decision tree along sequentially split branch paths from the highest priority leaf node toward the root node, the pointer code of the next immediately adjacent upstream node will always point to the node-branch path leading to the highest priority leaf node. Thus, the root node will point to the leaf node having the highest transmission priority.

    摘要翻译: 可由基于时分多路复用(TDM)的通信系统的控制处理器执行的基于二进制决策树的仲裁方案可操作以从多个虚拟电路中选择要发送的下一个分组,其中任意数量的虚拟电路可以具有一个或 更多的分组正在等待通过串行数字通信链路传输。 传输优先级方案包含N + 1个包含2个N + 1个-1节点的节点。 第i组节点包括2个节点,其中i大于或等于1,小于等于N + 1。 给定集合的节点通过二进制分割分支连接到相邻集合的节点。 对于决策树的2个N 2个节点中的每一个,存储代表从其相关联的通信端口等待发送的分组的传输优先级的信息。 此外,与分支到相应的下游节点对(朝向虚拟电路端口)的每个节点相关联的是指向其两个分支节点中的哪一个与较高分组传输优先级相关联的“指针”代码。 当沿着从最高优先级叶节点到根节点的顺序拆分分支路径遍历决策树时,下一个紧邻的上游节点的指针代码将总是指向通向最高优先级叶节点的节点 - 分支路径。 因此,根节点将指向具有最高传输优先级的叶节点。

    Integrated RF loopback test apparatus for redundant data radio transceiver system
    79.
    发明授权
    Integrated RF loopback test apparatus for redundant data radio transceiver system 有权
    用于冗余数据无线电收发系统的集成式RF环回测试仪

    公开(公告)号:US06996057B2

    公开(公告)日:2006-02-07

    申请号:US09971451

    申请日:2001-10-05

    IPC分类号: H04L12/26

    摘要: A redundant communication system contains a principal transceiver and a back-up transceiver to be controllably substituted for the principal transceiver. A monitor protection switch, which controls swapping the two transceivers, has an RF loopback test circuit that is switchably coupled to whichever transceiver is the back-up. The RF loopback test circuit monitors the operational capability of the back-up transceiver, and provides an indication of its functionality. If the back-up transceiver is defective, corrective action can be taken in advance of a potential operational failure of the principal transceiver. As long as the RF loopback test circuit indicates proper operational capability of the back-up transceiver, the redundant transceiver can be immediately switched in place of the principal transceiver.

    摘要翻译: 冗余通信系统包含主要收发器和可控制地代替主收发器的备用收发器。 控制交换两个收发器的监视器保护开关具有RF回路测试电路,其可切换地耦合到无论哪个收发器是备份。 RF环回测试电路监视备用收发器的操作能力,并提供其功能的指示。 如果备用收发器有缺陷,则可以在主收发器的潜在操作故障之前采取纠正措施。 只要RF环回测试电路指示备用收发器的正常操作能力,可以立即切换冗余收发器来代替主收发器。

    Technique for fault isolation and transient load isolation for multiple electrical loads connected to a common electrical power source
    80.
    发明授权
    Technique for fault isolation and transient load isolation for multiple electrical loads connected to a common electrical power source 有权
    用于连接到公共电源的多个电气负载的故障隔离和瞬态负载隔离技术

    公开(公告)号:US06982860B2

    公开(公告)日:2006-01-03

    申请号:US10293141

    申请日:2002-11-13

    IPC分类号: H01C7/12

    CPC分类号: H04M3/18 H02H9/025

    摘要: A central office transceiver-installed current limiter and regulator provides fault isolation and transient load isolation in a wireline communication network, having multiple transceivers connected by respective span-powered wirelines to a common power source at the central office. Using a current-sense resistor and controlled switch in series with the wireline, the current-limiter and regulator processes input electrical power from the power source prior to coupling that power to a remote transceiver. To prevent overheating and substantial power dissipation in the current-limiting circuitry in the event of a prolonged fault condition, the controlled switch is alternately turned on and off.

    摘要翻译: 中心局收发器安装的限流器和调节器在有线通信网络中提供故障隔离和瞬时负载隔离,其具有通过相应的跨功率有线线路连接到中心局的公共电源的多个收发器。 使用电流检测电阻和与电缆串联的受控开关,电流限制器和调节器在将该功率耦合到远程收发器之前,将来自电源的输入电功率进行处理。 为了防止在长时间故障情况下限流电路中的过热和实质的功率消耗,受控开关交替地接通和关断。