公开(公告)号：US07924791B2

公开(公告)日：2011-04-12

申请号：US11019436

申请日：2004-12-21

Applicant: Anca-Marina Ianos

Inventor： Anca-Marina Ianos

IPC: H04Q7/24

CPC classification number: H04W88/04 ,  H04W8/26 ,  H04W84/20

Abstract: A method of transmitting data packets within a local network including a master unit and at least two slave units is adapted to a configuration according to which the master unit comprises two processors. The first processor executes an application and the second processor controls a transmission of data between the master unit and any one of the slave units. According to the method, data packets sent by a first slave unit to a second slave unit pass through the second processor and are forwarded directly in accordance with a readdressing directive obtained from addressing elements which are interassociated and communicated by the first processor to the second processor.

Abstract translation: 在包括主单元和至少两个从单元的本地网络内传输数据分组的方法适用于主单元包括两个处理器的配置。 第一处理器执行应用，第二处理器控制主单元和任一个从单元之间的数据传输。 根据该方法，由第一从单元发送到第二从单元的数据分组通过第二处理器，并且根据从由第一处理器相互关联并传送到第二处理器的寻址元素获得的再调用指令直接转发 。

公开(公告)号：US07919864B2

公开(公告)日：2011-04-05

申请号：US10791136

申请日：2004-03-02

Applicant: Jacky Seiller ,  Jean-François Revel ,  Claude Douce

Inventor： Jacky Seiller ,  Jean-François Revel ,  Claude Douce

IPC: H01L29/40 ,  H01L21/4763

CPC classification number: H01L24/05 ,  H01L23/5227 ,  H01L23/5283 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit including one or several metallization levels, metal conductive strips and metal contact pads being formed on the last metallization level, the last level being covered with a passivation layer in which are formed openings above the contact pads. The thickness of the pads, at least at the level of their portions not covered by the passivation layer, is smaller than the thickness of said conductive strips.

Abstract translation: 包括一个或几个金属化水平的集成电路，金属导电条和金属接触焊盘在最后的金属化水平上形成，最后一个层被钝化层覆盖，其中在接触焊盘上形成开口。 至少在其未被钝化层覆盖的部分的水平面上的焊盘的厚度小于所述导电条的厚度。

公开(公告)号：US07902859B2

公开(公告)日：2011-03-08

申请号：US12579951

申请日：2009-10-15

Applicant: Nicolas Ricard ,  Laurent Jean Garcia

Inventor： Nicolas Ricard ,  Laurent Jean Garcia

IPC: H03K17/16 ,  H03K19/003

CPC classification number: G05F1/567 ,  H03F1/56

Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor.

Abstract translation: 电路包括具有耦合在第一电源电压和输出节点之间的第一可变电阻块的输出电路，所述第一可变电阻块具有与所述第一电源电压和所述输出之间的至少一个电阻器串联耦合的多个可选择的电阻元件 所述输出电路具有由所述第一可变电阻块的电阻确定的输出阻抗; 以及用于调节输出电路的第一可变电阻块的阻抗的补偿电路，所述补偿电路具有耦合在第一电源电压和外部电阻器的第一节点之间的第二可变电阻块，外部电阻器的第二节点 耦合到第二电源电压，其中所述第二可变电阻块包括与所述第一电源电压和所述外部电阻器的所述第一节点之间的至少一个电阻器串联耦合的多个可选择的电阻元件，并且其中所述多个可选择的电阻 基于外部电阻器的第一节点处的电压电平来选择第一和第二可变电阻块的元件。

公开(公告)号：US20110053053A1

公开(公告)日：2011-03-03

申请号：US12679266

申请日：2008-09-18

Applicant: Sébastien Desplobain ,  Gaël Gautier

Inventor： Sébastien Desplobain ,  Gaël Gautier

IPC: H01M8/02 ,  H01M8/00

CPC classification number: H01M8/1097 ,  H01M8/0232 ,  H01M8/04089 ,  H01M2008/1095

Abstract: A porous silicon wafer including, on its upper surface side, multiple recesses, this upper surface being coated with a porous silicon layer having pores smaller than those of the wafer bulk.

Abstract translation: 一种多孔硅晶片，在其上表面上包括多个凹槽，该上表面涂覆有具有小于晶片块的孔的多孔硅层。

公开(公告)号：US20110032032A1

公开(公告)日：2011-02-10

申请号：US12849270

申请日：2010-08-03

Applicant: Vincent Pinon

Inventor： Vincent Pinon

IPC: H03F1/26

CPC classification number: H03F1/3294 ,  H03F1/0233 ,  H03F1/3247

Abstract: An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and comprising a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier.

Abstract translation: 一种用于对要由具有可变电源电压的功率放大器放大的输入信号施加预失真增益的自适应预失真器，所述预失真器包括：适于将复增益应用于复输入信号的预失真增益块; 第一表，其在第一存储器中实现并且包括存储复增益值的单元的二维阵列，所述第一表适于基于所述输入信号的幅度和所述可变电源电压的值输出所述复增益值 功率放大器; 以及第二表，其在第二存储器中实现，并且包括存储用于更新第一表的复数增益值的增益更新值的单元的二维阵列，所述增益更新值是基于所述功率放大器的输出信号生成的。

公开(公告)号：US07875915B2

公开(公告)日：2011-01-25

申请号：US11432675

申请日：2006-05-10

Applicant: François Roy ,  Arnaud Tournier

Inventor： François Roy ,  Arnaud Tournier

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L27/1443 ,  H01L27/14609

Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.

Abstract translation: 集成电路包括与读取晶体管相关联的至少一个光电二极管。 光电二极管由包括掩埋层，浮置衬底层和上层的三个半导体层的堆叠形成。 晶体管的漏极区域和/或源极区域被并入上层。 掩埋层与上层电隔离，以便允许掩埋层独立于上层被偏置。

公开(公告)号：US20110006721A1

公开(公告)日：2011-01-13

申请号：US12521808

申请日：2008-01-04

Applicant: Laurent Gonthier ,  Raynald Achart

Inventor： Laurent Gonthier ,  Raynald Achart

IPC: H02P1/40

CPC classification number: H02P25/04 ,  H02P1/445

Abstract: The invention relates to a device for controlling the speed and the rotation direction of an asynchronous motor (1), comprising a first circuit (7) with two bi-directional switches (T′4, T′5) individually controlled and having first conducting terminals connected to a common terminal (6) for applying a direct potential (Vcc) and having second conducting terminals that can be respectively connected to the first ends (12, 14) of windings (15, 16) of the motor stator, and a second circuit (3′) with at least two parallel bi-directional switches (T1, T2, T3) individually controlled and having first respective conducting terminals (Ki) connected to the common terminal.

Abstract translation: 本发明涉及一种用于控制异步电动机（1）的速度和旋转方向的装置，包括具有单独控制并具有第一导通的两个双向开关（T'4，T'5）的第一电路（7） 连接到用于施加直接电位（Vcc）的公共端子（6）的端子，并具有可分别连接到电动机定子的绕组（15,16）的第一端（12,14）的第二导电端子，以及 具有至少两个并联的双向开关（T1，T2，T3）的第二电路（3'）被单独控制并且具有连接到公共端子的第一相应的导通端子（Ki）。

公开(公告)号：US20100289106A1

公开(公告)日：2010-11-18

申请号：US12781489

申请日：2010-05-17

Applicant: Jorge Regolini ,  Michael Gros-Jean

Inventor： Jorge Regolini ,  Michael Gros-Jean

IPC: H01L31/06 ,  H01L21/76

CPC classification number: H01L31/102 ,  H01L27/1446 ,  H01L27/1463 ,  H01L31/0352 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photodiode includes a first doped layer and a second doped layer that share a common face. A deep isolation trench has a face contiguous with the first and second doped layers. A conducting layer is in contact with a free face of the second doped layer. A protective layer is provided at an interface with the first doped layer and second doped layer. This protective layer is capable of generating a layer of negative charge at the interface. The protective layer may further be positioned within the second doped layer to form an intermediate protective structure.

Abstract translation: 光电二极管包括共享公共面的第一掺杂层和第二掺杂层。 深隔离沟槽具有与第一和第二掺杂层相邻的面。 导电层与第二掺杂层的自由面接触。 在与第一掺杂层和第二掺杂层的界面处提供保护层。 该保护层能够在界面处产生负电荷层。 保护层可以进一步定位在第二掺杂层内以形成中间保护结构。

公开(公告)号：US07820494B2

公开(公告)日：2010-10-26

申请号：US11713543

申请日：2007-03-02

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L21/338

CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/806 ,  H01L29/872 ,  H01L29/8725

Abstract: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging a peripheral trench and the trenches of the component; isotropically etching the first material so that a cap overhanging a recess remains; forming a thin insulating layer; and filling the trenches and said recess with a conductive material.

Abstract translation: 一种用于形成其外围由填充有导体的绝缘壁形成沟槽的TMBS型的部件的方法，包括以下步骤：在半导体衬底上沉积厚层的第一绝缘材料和第二材料的薄层; 同时挖掘周边沟槽和部件的沟槽; 各向同性蚀刻第一材料，使得悬挂在凹部上的盖保留; 形成薄的绝缘层; 并用导电材料填充沟槽和凹槽。

公开(公告)号：US20100245329A1

公开(公告)日：2010-09-30

申请号：US12793487

申请日：2010-06-03

Applicant: Jean-Raphael Bezal ,  Gilles Troussel ,  Jean-Marie Permezel

Inventor： Jean-Raphael Bezal ,  Gilles Troussel ,  Jean-Marie Permezel

IPC: G09G3/28 ,  G06F3/038

CPC classification number: G09G3/2965

Abstract: A method and circuit to control a circuit for addressing at least one line electrode of a plasma display panel having, for each line, a line selection stage formed of two switches in series between two input terminals of the selection stage, the method including alternating use of the two switches of the selection stage of each line to flow a current from or to an inductive element of the addressing circuit without connecting the input terminals together.

Abstract translation: 一种用于控制用于寻址等离子体显示面板的至少一个线电极的电路的方法和电路，所述等离子体显示面板的每一行具有由选择级的两个输入端之间串联的两个开关构成的线选择级，所述方法包括交替使用 的每一行的选择级的两个开关，以将电流从寻址电路的电感元件流到或不连接到输入端。