公开(公告)号：US07487414B2

公开(公告)日：2009-02-03

申请号：US11500126

申请日：2006-08-07

申请人： Hi-Choon Lee

发明人： Hi-Choon Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C29/44 ,  G11C2029/2602

摘要： An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.

摘要翻译： 集成电路装置包括测试电路和至少一个标志发生器电路。 测试电路被配置为响应于存储器测试操作并行地产生第一和第二组测试结果。 第一组和第二组测试结果分别对应于第一和第二存储体。 测试电路还被配置为将第一组测试结果中的相应测试结果与第二组测试结果中的相应测试结果合并，以向集成电路设备的一组输出终端中的相应测试结果提供一组合并的测试结果。 所述至少一个标志发生器电路被配置为产生指示在所述第一组测试结果中存在至少一个存储器测试错误的第一标志信号，以及指示存在至少一个存储器测试错误的第二标志信号 在第二组测试结果中。 基于合并的测试结果集合和第一和第二标志信号，测试电路可以确定第一和第二存储器组中的哪些存储块包括其中的有缺陷的存储单元。 还讨论了相关方法。

公开(公告)号：US07472326B2

公开(公告)日：2008-12-30

申请号：US10431043

申请日：2003-05-06

申请人： John M. Holmes

发明人： John M. Holmes

IPC分类号： G01R31/28

CPC分类号： G11C29/56 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/31926 ,  G11C29/56004 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to concurrently execute multiple programs on multiple test sites using a single pattern generator. In one embodiment, up to eight test programs are run independently and concurrently on eight independent sixteen-pin devices on a 128 pin test site. When the multitasking APG is ready to broadcast to a device, timing system associated with that device only (and not the other devices) are loaded. While the timing system is executing the cycle of the test programs for the device just loaded, the APG continues on to load the other devices. Because of the slow cycle rates required for programming versus reading, the tester is particularly advantageous for testing flash memory. Optionally, for higher throughput, the APG can be run in lock step at up to a maximum operating frequency of the APG during read cycle of flash.

摘要翻译： 提供了一种用于测试半导体器件的测试器和方法。 通常，测试器包括多任务算法模式生成器（APG），以使用单个模式生成器在多个测试站点上同时执行多个程序。 在一个实施例中，多达八个测试程序在128引脚测试站点上的八个独立的十六引脚器件上独立并行地运行。 当多任务APG准备好广播到设备时，仅加载与该设备相关联的定时系统（而不是其他设备）。 当定时系统正在执行刚装载的设备的测试程序周期时，APG继续加载其他设备。 由于编程与读取所需的循环速度慢，因此测试仪对闪存的测试特别有利。 可选地，为了更高的吞吐量，在闪存的读取周期期间，APG可以以高达APG的最大工作频率的锁定步进运行。

公开(公告)号：US07466612B2

公开(公告)日：2008-12-16

申请号：US11927913

申请日：2007-10-30

申请人： Young Bo Shim

发明人： Young Bo Shim

IPC分类号： G11C7/00

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device provided with a bank including N memory cell blocks and sense amplifiers, the method comprising the steps of: a) expressing the N memory cell blocks as a first, a second, . . . , an Nth memory cell block; b) sequentially activating odd-numbered memory cell blocks of the N memory cell blocks one by one in a predetermined time period; c) performing sense, read (or write) and precharge operations for each activated memory cell block; and d) performing steps a) to c) for even-numbered memory cell blocks after tests for all the odd-numbered memory cell blocks are finished.

摘要翻译： 公开了一种用于测试存储器件的方法，该存储器件可以在测试另一存储器单元块的同时测试存储器单元块，以便在短时间内捕获存储器件的工艺缺陷，从而减少测试时间。 一种用于测试具有包括N个存储单元块和读出放大器的存储体的存储器件的方法，所述方法包括以下步骤：a）将N个存储单元块表示为第一，第二， 。 。 ，第N个存储单元块; b）在预定时间段内依次激活N个存储单元块的奇数存储单元块; c）为每个激活的存储器单元块执行读取（或写入）和预充电操作; 以及d）对于所有奇数存储单元块的测试结束之后，对偶数存储单元块执行步骤a）至c）。

公开(公告)号：US20080304345A1

公开(公告)日：2008-12-11

申请号：US12005441

申请日：2007-12-26

申请人： Ki-Chang Kwean

发明人： Ki-Chang Kwean

IPC分类号： G11C29/48

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled.

摘要翻译： 半导体存储器件包括多个存储体，用于输入和输出数据的数据引脚，以及连接到数据引脚的输入/输出缓冲器。 每个存储体具有用于存储数据的多个存储单元。 数据引脚由引脚选择信号使能和禁止。 当引脚选择信号被使能时，数据引脚执行正常的数据输入/输出操作，当引脚选择信号被禁止时，连接到数据引脚的终端电阻关闭。 当禁止引脚选择信号时，输入/输出缓冲器使一个连接到数据引脚的终端电阻关闭。

公开(公告)号：US07434125B2

公开(公告)日：2008-10-07

申请号：US11415443

申请日：2006-05-01

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R31/28

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.

摘要翻译： 提供了一种集成电路，该集成电路具有用于根据测试模式从集成电路读出错误数据的测试电路，其中该误差数据经由第一和第二数据输出被输出，并且其中一个地址和 读取命令被应用于集成电路，以通过数据输出之一读出与地址相关联的错误数据。 测试电路被配置成使得当应用第一读取命令时，测试电路在第一数据输出处输出误差数据并将第二数据输出切换为高阻抗，并且当应用第二读取命令时， 测试电路在第二个数据输出端输出误差数据，并将第一个数据输出切换到高阻抗。

公开(公告)号：US20080192562A1

公开(公告)日：2008-08-14

申请号：US11961998

申请日：2007-12-20

申请人： Hong-Sok Choi

发明人： Hong-Sok Choi

IPC分类号： G11C8/00

CPC分类号： G11C29/34 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/2602

摘要： A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.

摘要翻译： 半导体存储装置的列地址解码电路包括：预解码器，被配置为组合列地址和解码测试信号，从而输出解码地址。 主解码器接收解码地址，从而输出多个列选择信号。

公开(公告)号：US07411847B2

公开(公告)日：2008-08-12

申请号：US11041829

申请日：2005-01-24

申请人： Esin Terzioglu ,  Gil I. Winograd

发明人： Esin Terzioglu ,  Gil I. Winograd

IPC分类号： G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/2602

摘要： The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

摘要翻译： 本发明涉及并行地应用分层存储器结构的系统和方法，测试弱缺陷的存储器结构。 本发明包括将逻辑0写入到存储器结构中的所有存储单元中。 所有高地址预编码线路和最低地址的交替预编码线路都被使能。 相邻字线和位线之间的电压降受到影响。 逻辑I被写入存储器结构中的所有存储器单元。 由于存储器单元中的逻辑1，在位线上产生相反的电压极性。 通过翻转最低预编码行的状态（即，通过改变对应于该行的输入地址），在字线上实现反向电压极性应力。

公开(公告)号：US20080165596A1

公开(公告)日：2008-07-10

申请号：US12000648

申请日：2007-12-14

申请人： Kwun-soo Cheon ,  Chang-yong Lee ,  Won-kyung Chung

发明人： Kwun-soo Cheon ,  Chang-yong Lee ,  Won-kyung Chung

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/34 ,  G11C29/1201 ,  G11C2029/0405 ,  G11C2029/2602

摘要： A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.

摘要翻译： 提供一种半导体存储器件及其方法。 示例性半导体存储器件可以包括包括多个存储器单元的存储单元阵列，期望数据生成单元在存储器操作期间通过至少一个地址焊盘接收多个初始期望数据，并且基于该存储器单元产生多个预期数据 多个初始预期数据，所述至少一个地址焊盘与数据输入/输出焊盘分离，并且并行位测试电路基于多个读取数据和多个预期数据产生测试结果数据。

公开(公告)号：US20080159031A1

公开(公告)日：2008-07-03

申请号：US12049110

申请日：2008-03-14

申请人： Khaled Fekih-Romdhane

发明人： Khaled Fekih-Romdhane

IPC分类号： G11C29/36

CPC分类号： G11C29/26 ,  G11C11/401 ,  G11C29/40 ,  G11C2029/2602

摘要： Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of data lines required for transmitting compressed test data. Data lines effectively freed up due to compression of test data read from one bank may be used to carry test data for another bank.

摘要翻译： 提供了通过允许同时访问多个存储体来增加前端测试吞吐量的方法和装置。 本文描述的技术利用了传送压缩测试数据所需的数据线数目的减少。 由于从一个银行读取的测试数据的压缩而有效地释放的数据线可以用于携带另一个银行的测试数据。

公开(公告)号：US07394268B2

公开(公告)日：2008-07-01

申请号：US11531140

申请日：2006-09-12

申请人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

发明人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

IPC分类号： G01R31/02

CPC分类号： G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

摘要翻译： 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。