公开(公告)号：US08634265B2

公开(公告)日：2014-01-21

申请号：US12814702

申请日：2010-06-14

申请人： Kwi-Dong Kim ,  Ki-Chang Kwean

发明人： Kwi-Dong Kim ,  Ki-Chang Kwean

IPC分类号： G11C17/18

CPC分类号： G11C16/16 ,  G11C16/18

摘要： A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.

摘要翻译： 一种半导体存储器件，包括：信息存储单元，包括被配置为存储信息的熔丝;控制单元，被配置为响应于控制脉冲信号控制熔断熔丝的节点变为浮置状态;以及输出单元， 信息。

公开(公告)号：US20120284470A1

公开(公告)日：2012-11-08

申请号：US13548117

申请日：2012-07-12

申请人： Ji-Hyae Bae ,  Sang-Sik Yoon ,  Ki-Chang Kwean

发明人： Ji-Hyae Bae ,  Sang-Sik Yoon ,  Ki-Chang Kwean

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F13/4243 ,  G11C29/08 ,  G11C29/10 ,  G11C29/12015

摘要： Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

摘要翻译： 具有高速数据传输能力的半导体存储器件，具有相同的半导体存储器件包括多个地址输入电路和多个数据输出电路，以及训练驱动器，被配置为将通过多个地址输入电路输入的地址信息与数据 加载用于读取训练的信号，并且生成要通过多个数据输出电路输出的数据训练模式。

公开(公告)号：US20100254200A1

公开(公告)日：2010-10-07

申请号：US12816040

申请日：2010-06-15

申请人： Sun-Suk Yang ,  Ki-Chang Kwean

发明人： Sun-Suk Yang ,  Ki-Chang Kwean

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C11/406 ,  G11C11/40611 ,  G11C2211/4061

摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.

摘要翻译： 具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器 在自动刷新缓冲控制器的数据训练操作中产生。

公开(公告)号：US07760557B2

公开(公告)日：2010-07-20

申请号：US12005573

申请日：2007-12-27

申请人： Sun-Suk Yang ,  Ki-Chang Kwean

发明人： Sun-Suk Yang ,  Ki-Chang Kwean

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C11/406 ,  G11C11/40611 ,  G11C2211/4061

摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.

摘要翻译： 具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器 在自动刷新缓冲控制器的数据训练操作中产生。

公开(公告)号：US07679981B2

公开(公告)日：2010-03-16

申请号：US12409095

申请日：2009-03-23

申请人： Hyung Wook Moon ,  Ki Chang Kwean

发明人： Hyung Wook Moon ,  Ki Chang Kwean

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618

摘要： A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state.

摘要翻译： 半导体器件可以包括第一逻辑单元，用于执行关于多个第一控制信号的逻辑运算，每个第一控制信号指示半导体器件的多个存储体中的对应一个是处于活动状态，刷新检测器 用于输出当至少一个存储体执行自刷新操作或自动刷新操作时使能的第二控制信号，以及用于对来自第一逻辑单元的输出信号进行逻辑运算的第二逻辑单元，以及 所述第二控制信号产生具有关于所述半导体器件的激活的信息的第三控制信号。 当至少一个存储体执行自刷新操作或自动刷新操作（即使处于活动状态）时，第三控制信号被使能。

公开(公告)号：US07538601B2

公开(公告)日：2009-05-26

申请号：US11647777

申请日：2006-12-28

申请人： Ki Chang Kwean

发明人： Ki Chang Kwean

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07 ,  H02M2001/0012

摘要： A step-up voltage generator for a semiconductor memory is provided which includes a level detection unit, a bank-active command generator, and an oscillation signal generator. The level detection unit compares a reference voltage with a division voltage of a pumping voltage, detects a level of the pumping voltage according to the comparison result, and generates a level detection signal. The bank-active command generator generates bank-active signals in response to a row-active command signal. The oscillation signal generator determines whether it received the bank-active signals from the bank-active command generator, replies to the bank-active signals or the level detection signal according to the determination result, and generates oscillation signals. An active-voltage UP converter performs pumping of a power-supply voltage in response to the oscillation signals, and generates a step-up voltage.

摘要翻译： 提供一种用于半导体存储器的升压电压发生器，其包括电平检测单元，存储体激活命令发生器和振荡信号发生器。 电平检测单元将参考电压与泵浦电压的分压相比较，根据比较结果检测泵浦电压的电平，并产生电平检测信号。 存储体激活命令发生器响应于行活动命令信号产生存储体活动信号。 振荡信号发生器根据确定结果确定是否接收到来自存储体激活命令发生器的存储体激活信号，根据确定结果回应存储体激活信号或电平检测信号，并产生振荡信号。 有源电压UP转换器响应于振荡信号执行电源电压的泵浦，并产生升压电压。

公开(公告)号：US07057966B2

公开(公告)日：2006-06-06

申请号：US10998678

申请日：2004-11-30

申请人： Shin-Deok Kang ,  Ki-Chang Kwean

发明人： Shin-Deok Kang ,  Ki-Chang Kwean

IPC分类号： G11C8/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/418

摘要： A synchronous memory device can reduce unnecessary current consumption in its operation. In the synchronous memory device, a clock receiver receives an external clock to output a first internal clock. An address latch unit receives and latches an address in synchronous with the first internal clock. A row address latch unit latches a row address that is outputted from the address latch unit. A column address control unit receives the first internal clock to output a second internal clock and stops the output of the second internal clock when a non-column command is performed. Finally, a column address control unit is activated in response to the second internal clock to count a column address that is outputted from the address latch unit so as to output an inner column address.

摘要翻译： 同步存储器件可以在其操作中减少不必要的电流消耗。 在同步存储器件中，时钟接收器接收外部时钟以输出第一内部时钟。 地址锁存单元接收并锁存与第一内部时钟同步的地址。 行地址锁存单元锁存从地址锁存单元输出的行地址。 列地址控制单元接收第一内部时钟以输出第二内部时钟，并且当执行非列命令时停止第二内部时钟的输出。 最后，列地址控制单元响应于第二内部时钟被激活，以对从地址锁存单元输出的列地址进行计数，以输出内列地址。

公开(公告)号：US20050140969A1

公开(公告)日：2005-06-30

申请号：US10998678

申请日：2004-11-30

申请人： Shin-Deok Kang ,  Ki-Chang Kwean

发明人： Shin-Deok Kang ,  Ki-Chang Kwean

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/418

摘要： A synchronous memory device can reduce unnecessary current consumption in its operation. In the synchronous memory device, a clock receiver receives an external clock to output a first internal clock. An address latch unit receives and latches an address in synchronous with the first internal clock. A row address latch unit latches a row address that is outputted from the address latch unit. A column address control unit receives the first internal clock to output a second internal clock and stops the output of the second internal clock when a non-column command is performed. Finally, a column address control unit is activated in response to the second internal clock to count a column address that is outputted from the address latch unit so as to output an inner column address.

摘要翻译： 同步存储器件可以在其操作中减少不必要的电流消耗。 在同步存储器件中，时钟接收器接收外部时钟以输出第一内部时钟。 地址锁存单元接收并锁存与第一内部时钟同步的地址。 行地址锁存单元锁存从地址锁存单元输出的行地址。 列地址控制单元接收第一内部时钟以输出第二内部时钟，并且当执行非列命令时停止第二内部时钟的输出。 最后，列地址控制单元响应于第二内部时钟而被激活，以对从地址锁存单元输出的列地址进行计数，以输出内列地址。

公开(公告)号：US06909643B2

公开(公告)日：2005-06-21

申请号：US10749353

申请日：2003-12-31

申请人： Ki-Chang Kwean

发明人： Ki-Chang Kwean

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1093 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A data strobe circuit for prefetching M number of N bit data, N and M being a positive integer, includes a data strobe buffering unit for generating N number of align control signals based on a data strobe signal; a synchronizing block having M number of latch blocks, each for receiving N bit data and outputting the N−1 bit data in a parallel fashion in response to N−1 number of the align control signals and one bit prefetched data in response to the remaining align control signals; and a output block having M number of aligning blocks, each for receiving the N−1 bit data in the parallel fashion, synchronizing the N−1 bit data with the align control signal and outputting the synchronized N−1 bit data as the N−1 bit prefetched data.

摘要翻译： 一种数据选通电路，用于预取M个N位数据，N和M为正整数，包括数据选通缓冲单元，用于基于数据选通信号产生N个对准控制信号; 具有M个锁存块的同步块，每个用于接收N位数据并且响应于N-1个对准控制信号并且响应于剩余的一个比特预取数据以并行方式输出N-1个比特数据 调整控制信号; 以及具有M个对准块的输出块，每个用于以并行方式接收N-1位数据，使N-1位数据与对齐控制信号同步，并将同步的N-1位数据作为N- 1位预取数据。

公开(公告)号：US20050013191A1

公开(公告)日：2005-01-20

申请号：US10746032

申请日：2003-12-24

申请人： Ki Chang Kwean

发明人： Ki Chang Kwean

IPC分类号： G11C7/10 ,  G11C5/06 ,  G11C8/00

CPC分类号： G11C5/063

摘要： Disclosed is a memory device having repeaters capable of preventing an expected signal delay and a signal distortion caused by a long transmission length of a long address signal and a long control signal. The memory device comprises: a plurality of banks; an address pad; an address driver for transmitting an address signal, which is inputted through the address pad, into each of the banks through address signal lines; a control pad; a control driver for transmitting a control signal, which is inputted through the control pad, into each of the banks through control signal lines; and repeaters arranged on the address signal lines and/or the control signal lines.

摘要翻译： 公开了具有能够防止由长地址信号和长控制信号的长传输长度引起的预期信号延迟和信号失真的中继器的存储器件。 存储装置包括：多个存储体; 地址栏 地址驱动器，用于通过地址信号线将通过地址块输入的地址信号发送到每个存储体; 控制板 控制驱动器，用于通过控制信号线将通过控制焊盘输入的控制信号发送到每个存储体; 以及布置在地址信号线和/或控制信号线上的中继器。