公开(公告)号：US08537952B1

公开(公告)日：2013-09-17

申请号：US12044532

申请日：2008-03-07

Applicant: Himanshu Arora

Inventor： Himanshu Arora

IPC: H03D3/24

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03L7/089 ,  H03L7/1974

Abstract: A fractional-N PLL uses separate charge pumps under the control of separate frequency and phase detectors. Phase jitter from an N divider is linearized by the use of a circuit that generates pulses from the output of the N divider. After frequency lock, the frequency detector turns off the frequency charge pump. After phase lock, activity in the phase detector down charge pump is minimized, reducing the overall noise produced by respective phase and frequency detector charge pumps.

Abstract translation: 分数N PLL在单独的频率和相位检测器的控制下使用单独的电荷泵。 来自N分频器的相位抖动通过使用从N分频器的输出产生脉冲的电路进行线性化。 频率锁定后，频率检测器关闭频率电荷泵。 锁相后，相位检测器下降电荷泵的活动最小化，降低了相位和频率检测器电荷泵产生的整体噪声。

公开(公告)号：US08174326B1

公开(公告)日：2012-05-08

申请号：US11590361

申请日：2006-10-30

Applicant: Shuliang Li

Inventor： Shuliang Li

IPC: H03L7/08 ,  H03C3/06

CPC classification number: H03C3/0925 ,  H03C3/0933

Abstract: In one embodiment, a cross zero best error selection system includes an error input interface, a most significant bit summation component and a multiplexer. The error input interface in coupled to a most significant bit summation component which in turn is coupled to a multiplexer. The error input interface receives a plurality of future error values. The most significant bit summation component sums most significant bits of said future error values. The multiplexer for selects error value based upon said summation of said most significant bits.

Abstract translation: 在一个实施例中，交叉零最佳误差选择系统包括误差输入接口，最高有效位求和分量和多路复用器。 误差输入接口耦合到最高有效位求和分量，其又耦合到多路复用器。 错误输入接口接收多个未来的错误值。 最高有效位求和分量将所述未来误差值的最高有效位相加。 所述多路复用器用于基于所述最高有效位的所述求和来选择误差值。

公开(公告)号：US08040996B2

公开(公告)日：2011-10-18

申请号：US12192988

申请日：2008-08-15

Applicant: Alireza Zolfaghari

Inventor： Alireza Zolfaghari

IPC: H03D3/24 ,  H04K3/00

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03D3/241 ,  H03L7/193 ,  H03L7/1976

Abstract: Aspects of a method and system for RF signal generation utilizing a synchronous multi-modulus divider are provided. In this regard, a feedback signal of a PLL may be generated by clocking a counter with an RF signal output by the PLL and toggling the feedback signal each time a determined value of the counter is reached. Moreover, updates of each register in the counter and transitions of the feedback signal may be synchronous with the RF signal output by the PLL. The PLL may be part of a cellular transmitter and/or receiver which may communicate over an EDGE network. A counting sequence of the counter may be determined, at least in part, by an output of a ΔΣ modulator. In this regard, a first counting sequence may be utilized when an output of the ΔΣ modulator may be asserted and a second counting sequence may be utilized when the output of ΔΣ modulator may be de-asserted.

Abstract translation: 提供了利用同步多模式分频器的用于RF信号产生的方法和系统的方面。 在这方面，PLL的反馈信号可以通过用PLL输出的RF信号对计数器计时并在每次达到计数器的确定值时触发反馈信号来产生。 此外，计数器中的每个寄存器的更新和反馈信号的转换可以与由PLL输出的RF信号同步。 PLL可以是可以通过EDGE网络通信的蜂窝发射机和/或接收机的一部分。 计数器的计数序列可以至少部分地由＆Dgr＆amp; Sgr的输出确定。 调制器。 在这方面，当“Dgr＆amp; S”的输出可以使用第一个计数序列。 调制器可以被断言，并且当Dgr＆amp; Sgr的输出可以使用第二计数序列。 调制器可能被取消断言。

公开(公告)号：US07982510B2

公开(公告)日：2011-07-19

申请号：US12573253

申请日：2009-10-05

Applicant: Arnaud Casagrande

Inventor： Arnaud Casagrande

IPC: H03L7/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991

Abstract: The frequency synthesizer for implementing a self-calibration method includes (i) a first phase lock loop comprising: a reference oscillator, a phase comparator, a first charge pump, a first loop filter, a voltage controlled oscillator, and a multimode divider counter controlled by a modulator and connected to the phase comparator; (ii) a high frequency access comprising a digital-analogue converter connected to an input of the voltage-controlled oscillator; (iii) a second charge pump connected to the phase comparator; and (iv) a second loop filter in the high frequency access. The second charge pump forms, when switched on, a second phase lock loop with the second loop filter. To calibrate gains of the converter, a voltage comparator compares an output voltage of the converter with a voltage stored in the second loop filter, after disconnecting the second charge pump from the second phase lock loop, previously locked onto a determined output frequency.

Abstract translation: 用于实现自校准方法的频率合成器包括：（i）第一锁相环，包括：参考振荡器，相位比较器，第一电荷泵，第一环路滤波器，压控振荡器和多模除法器控制 通过调制器连接到相位比较器; （ii）包括连接到所述压控振荡器的输入的数模转换器的高频接入; （iii）连接到相位比较器的第二电荷泵; 和（iv）高频接入中的第二环路滤波器。 第二个电荷泵在接通时形成具有第二环路滤波器的第二个锁相环。 为了校准转换器的增益，电压比较器将先前锁定到确定的输出频率上的第二电荷泵与第二锁相环断开之后，将转换器的输出电压与存储在第二环路滤波器中的电压进行比较。

公开(公告)号：US07979038B2

公开(公告)日：2011-07-12

申请号：US12160874

申请日：2007-01-16

Applicant: Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

Inventor： Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

IPC: H04B1/04

CPC classification number: H03L7/1976 ,  H03C3/0908 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

Abstract: Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation signal input means for inputting a first modulation signal to a divider (112) or a phase comparator (113) of the PLL unit (110); second modulation signal input means for DA converting the digital modulation signal in a DA converter (116) to generate an analog second modulation signal and inputting it to a voltage control oscillator (111) of the PLL unit (110); a second divider for dividing the output signal of the voltage control oscillator (111); and control means for generating a center frequency control signal, a gain control signal, and a second division ration control signal according to the channel selection signal and the control voltage inputted to the voltage control oscillator (111) and supplying them to the divider (112), the DA converter (116), and the second divider (114), respectively.

Abstract translation: 提供了能够维持宽带调制的调制精度的PLL调制电路，无线发送装置以及无线通信装置。 PLL调制电路（100）包括：PLL单元（110），用于将第一调制信号输入到PLL单元（110）的分频器（112）或相位比较器（113）的第一调制信号输入装置; 第二调制信号输入装置，用于在DA转换器（116）中转换数字调制信号，以产生模拟第二调制信号并将其输入到PLL单元（110）的电压控制振荡器（111）; 用于分压电压控制振荡器（111）的输出信号的第二分频器; 以及控制装置，用于根据输入到电压控制振荡器（111）的通道选择信号和控制电压产生中心频率控制信号，增益控制信号和第二分频控制信号，并将其提供给分频器（112） ），DA转换器（116）和第二分频器（114）。

公开(公告)号：US07974374B2

公开(公告)日：2011-07-05

申请号：US11749538

申请日：2007-05-16

Applicant: John B. Groe ,  Joe Austin ,  Damian Costa

Inventor： John B. Groe ,  Joe Austin ,  Damian Costa

IPC: H03D3/24

CPC classification number: H03C3/0925 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03C3/0933 ,  H03C3/0958

Abstract: Systems for multi-mode phase modulation are disclosed. Systems provide for direct modulation of a multi-mode voltage controlled oscillator (VCO). A fractional-N counter may be used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal. The multi-mode VCO may be characterized by a first frequency gain during operation in a first mode and by a second frequency gain during operation in a second mode where signals controlling the first and second operating modes are provided by a control circuit. The control circuit may include a switch to provide control signals to the VCO.

Abstract translation: 公开了用于多模相位调制的系统。 系统提供对多模式压控振荡器（VCO）的直接调制。 在锁相环（PLL）中可以使用分数N计数器来合成射频载波信号。 多模式VCO可以在第一模式下操作期间的第一频率增益和在控制第一和第二操作模式的信号由控制电路提供的第二模式中的第二频率增益来表征。 控制电路可以包括向VCO提供控制信号的开关。

公开(公告)号：US07940142B2

公开(公告)日：2011-05-10

申请号：US12506997

申请日：2009-07-21

Applicant: Henrik T. Jensen ,  Brima B. Ibrahim

Inventor： Henrik T. Jensen ,  Brima B. Ibrahim

IPC: H03C3/20 ,  H03C3/06

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/093

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract translation: 极性发射机包括用于产生宽带宽的RF信号的两点调制锁相环（PLL）。 PLL包括用于接收可变包络调制信号的相位信号并沿着第一信号路径提供相位信号以产生第一频率调制信号的第一输入端和用于接收相位信号并提供相位信号的第二输入端 用于产生第二频率调制信号的第二信号路径。 PLL还包括具有两个调制点的压控振荡器（VCO），一个用于接收第一频率调制信号，另一个用于接收第二频率调制信号。 VCO由第一频率调制信号和第二频率调制信号的集合控制，以将来自IF的相位信号上变频到RF以产生具有宽带宽的RF信号。

公开(公告)号：US07932787B1

公开(公告)日：2011-04-26

申请号：US11590385

申请日：2006-10-30

Applicant: Shuliang Li

Inventor： Shuliang Li

IPC: H03B29/00

CPC classification number: H03C3/0925 ,  H03C3/0933

Abstract: A phase-locked loop control system and method are described. Present invention phase-locked loop control systems and methods facilitate control of phase-lock loop operations. In one embodiment, phase-lock loop control systems and methods are utilized in the implementation of a modulated frequency synthesizer for facilitating efficient frequency spreading over a designated spectrum. It is appreciated that present invention embodiments can have a variety of implementations and can be compatible with vector accumulation. For example, a phase-locked loop control system or method can facilitate generation of a variety of modulation patterns, including but not necessarily limited to linear or non-linear modulation, standard or non-standard modulation, etc.

Abstract translation: 描述了锁相环控制系统和方法。 本发明的锁相环控制系统和方法便于控制锁相环操作。 在一个实施例中，锁相环控制系统和方法被用于实现调制频率合成器，以促进在指定频谱上的有效频率扩展。 应当理解，本发明实施例可以具有各种实施方式并且可以与矢量累积兼容。 例如，锁相环控制系统或方法可以促进各种调制模式的产生，包括但不必限于线性或非线性调制，标准或非标准调制等。

公开(公告)号：US07912109B1

公开(公告)日：2011-03-22

申请号：US11590433

申请日：2006-10-30

Applicant: Shuliang Li

Inventor： Shuliang Li

IPC: H04B1/00

CPC classification number: H03C3/0925 ,  H03C3/0933

Abstract: A frequency synthesizer is described illustrating a system and method for modulation. In particular, the frequency synthesizer includes a control circuit for producing a plurality of input signals that is scalable to a frequency profile. Each of the input signals includes a slope and a direction of the slope. An accumulator is coupled to the control circuit and receives the plurality of input signals. The accumulator sums the plurality of input signals to generate a standard curve. A frequency spreading control pattern generation modulator is coupled to the accumulator and modulates the standard curve to generate the desired frequency profile.

Abstract translation: 描述了用于调制的系统和方法的频率合成器。 特别地，频率合成器包括用于产生可以对频率分布进行扩展的多个输入信号的控制电路。 每个输入信号包括斜率和斜率方向。 累加器耦合到控制电路并接收多个输入信号。 累加器对多个输入信号求和以产生标准曲线。 频率扩展控制模式生成调制器耦合到累加器并调制标准曲线以产生所需的频率分布。

公开(公告)号：US07839230B2

公开(公告)日：2010-11-23

申请号：US12469252

申请日：2009-05-20

Applicant: Masakatsu Maeda ,  Takayuki Tsukizawa ,  Hiroyuki Yoshikawa ,  Shunsuke Hirano

Inventor： Masakatsu Maeda ,  Takayuki Tsukizawa ,  Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC: H03L5/00

CPC classification number: H03L7/099 ,  H03C3/04 ,  H03C3/0925 ,  H03C3/0933 ,  H03C5/00 ,  H03L5/00

Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.

Abstract translation: 提供了一种PLL振荡电路，其可以降低VCO 101的调制灵敏度的可变性，并以高精度快速获得期望的输出幅度。 振幅检测器103检测VCO 101的输出幅度。振幅控制器105控制可变电流源109的电流值，使振幅检测器103检测到的VCO 101的输出幅度为期望幅度。 LPF 108连接在振幅控制器105和可变电流源109之间。开关107连接或断开振幅控制器105和可变电流源109之间的LPF108。振幅控制器105连接到可变电流源109 通过LPF 108或切换开关107。