公开(公告)号：US06864746B2

公开(公告)日：2005-03-08

申请号：US10346918

申请日：2003-01-17

Applicant: Jonathon Cheah ,  Eng Chuan Low

Inventor： Jonathon Cheah ,  Eng Chuan Low

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/001 ,  H03F3/45201 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45386 ,  H03F2203/45506 ,  H03F2203/45728 ,  H03G1/0029 ,  H03G1/0088

Abstract: A dual gain amplification low noise amplifier that includes an amplification circuit to a provide dual gain amplification—high gain amplification for a weak data signal and low gain amplification for a strong data signal. Also included is a control circuit to maintain approximately the same P1dB point for the weak signal during high gain amplification as for the strong signal during low gain amplification.

Abstract translation: 双增益放大低噪声放大器，包括放大电路，为弱数据信号提供双增益放大 - 高增益放大，强数据信号提供低增益放大。 还包括一个控制电路，用于在高增益放大期间为弱信号保持大致相同的P1dB点，对于低增益放大期间的强信号。

公开(公告)号：US20050007197A1

公开(公告)日：2005-01-13

申请号：US10909097

申请日：2004-08-02

Applicant: Adel Fanous ,  Leonard Dauphinee ,  Lawrence Burns ,  Donald McMullin

Inventor： Adel Fanous ,  Leonard Dauphinee ,  Lawrence Burns ,  Donald McMullin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

CPC classification number: H03F3/45183 ,  H03F3/45201 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45464 ,  H03F2203/45466 ,  H03F2203/45638 ,  H03F2203/45696 ,  H03G1/0029 ,  H03G3/3036 ,  H03G3/3052

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

公开(公告)号：US06838937B2

公开(公告)日：2005-01-04

申请号：US10658837

申请日：2003-09-10

Applicant: Adel Fanous ,  Leonard Dauphinee ,  Lawrence M. Burns ,  Donald McMullin

Inventor： Adel Fanous ,  Leonard Dauphinee ,  Lawrence M. Burns ,  Donald McMullin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30 ,  H03F3/68

CPC classification number: H03F3/45183 ,  H03F3/45201 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45464 ,  H03F2203/45466 ,  H03F2203/45638 ,  H03F2203/45696 ,  H03G1/0029 ,  H03G3/3036 ,  H03G3/3052

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract translation: 提供了一种用于在放大模块中实现增益控制的系统，其包括具有多个第一级输入和输出端口的第一级放大器。 第一级放大器被配置为向接收到的输入信号提供第一级放大，并且从放大的输入信号产生多个输出信号。 还包括多个第二级放大器，每个具有第二级输入和输出端口，第二级输入端口分别耦合到第一级输出端口并且被配置为接收多个输出信号。 增益控制装置耦合到包括第一级输入端口，第一级输出端口和第二级输出端口的组中的至少一个。 增益控制装置还被配置为控制第一级放大器和多个第二级放大器中的至少一个的增益。

公开(公告)号：US06801085B2

公开(公告)日：2004-10-05

申请号：US10630870

申请日：2003-07-31

Applicant: Adel Fanous ,  Leonard Dauphinee ,  Lawrence M. Burns ,  Donald McMullin

Inventor： Adel Fanous ,  Leonard Dauphinee ,  Lawrence M. Burns ,  Donald McMullin

IPC: H03F368

CPC classification number: H03F3/45183 ,  H03F3/45201 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45464 ,  H03F2203/45466 ,  H03F2203/45638 ,  H03F2203/45696 ,  H03G1/0029 ,  H03G3/3036 ,  H03G3/3052

Abstract: A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers. Inverting output ports of each of the first group of amplifiers are coupled to a module inverting output terminal, and non-inverting output ports are coupled to a module non-inverting output terminal. A divider network is provided and is coupled to the input ports of the first group of amplifiers. A second group of amplifiers is also provided. Each amplifier of the second group corresponds to one of the amplifiers in the first group, has an inverting input port coupled to the second module inverting input terminal and to output ports of the divider network, and a non-inverting input port coupled to the second non-inverting input terminal. The inverting output ports of the second group of amplifiers are coupled to the inverting output terminal and non-inverting output ports of the second group of amplifiers are coupled to the non-inverting output terminal.

Abstract translation: 提供了用于激活放大模块中的增益级的系统。 该系统包括具有第一组放大器的放大模块。 第一组放大器中的每一个的反相输出端口耦合到模块反相输出端子，并且非反相输出端口耦合到模块非反相输出端子。 提供分频器网络并且耦合到第一组放大器的输入端口。 还提供了第二组放大器。 第二组的每个放大器对应于第一组中的一个放大器，具有耦合到第二模块反相输入端并且分配网络的输出端口的反相输入端口以及耦合到第二组的第二组的非反相输入端口 非反相输入端子。 第二组放大器的反相输出端口耦合到反相输出端子，并且第二组放大器的非反相输出端口耦合到非反相输出端子。

公开(公告)号：US06717472B2

公开(公告)日：2004-04-06

申请号：US10116500

申请日：2002-04-04

Applicant: Pieter Gerrit Blanken ,  Franciscus Adrianus Cornelis Maria Schoofs ,  Mike Hendrikus Splithof ,  Paulus Petrus Franciscus Maria Bruin

Inventor： Pieter Gerrit Blanken ,  Franciscus Adrianus Cornelis Maria Schoofs ,  Mike Hendrikus Splithof ,  Paulus Petrus Franciscus Maria Bruin

IPC: H03G320

CPC classification number: H03F3/3035 ,  H03F3/45201

Abstract: An electronic circuit comprising an amplifier includes an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (VSS, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises a controller adapted to prevent the output transistor (N2, P1) to enter its linear state whereby the controller is arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.

Abstract translation: 包括放大器的电子电路包括用于向负载提供输出信号（Vout）的输出端（OUT），所述放大器包括输出晶体管（N2，P1），其具有耦合到电源电压端子（VSS， VDD），耦合到输出端（OUT）的第二主端子和控制端子。 为了避免输出晶体管（N2，P1）进入其线性状态，这将导致放大器对于某些目的而不能接受地变慢，电子电路还包括控制器，其适于防止输出晶体管（N2，P1） 进入其线性状态，由此，当第二主端子和第一主端子之间的输出电压（Vout）低于限定电平时，控制器布置成用于减小控制端子与第一主端子之间的控制电压（Vcntr1）。

公开(公告)号：US20020158692A1

公开(公告)日：2002-10-31

申请号：US10116500

申请日：2002-04-04

Inventor： Pieter Gerrit Blanken ,  Franciscus Adrianus Cornelis Maria Schoofs ,  Mike Hendrikus Splithof ,  Paulus Petrus Franciscus Maria Bruin

IPC: H03F003/04

CPC classification number: H03F3/3035 ,  H03F3/45201

Abstract: An electronic circuit comprising an amplifier comprising an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (Vss, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises control means for avoiding the output transistor (N2, P1) to enter its linear state whereby the control means are arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.

Abstract translation: 一种电子电路，包括：放大器，包括用于向负载提供输出信号（Vout）的输出端（OUT），所述放大器包括输出晶体管（N2，P1），所述输出晶体管具有耦合到电源电压端子（Vss， VDD），耦合到输出端（OUT）的第二主端子和控制端子。 为了避免输出晶体管（N2，P1）进入其线性状态，这将导致放大器对于某些目的而不能接受地变慢，电子电路还包括用于避免输出晶体管（N2，P1）进入的控制装置 其线性状态，其中当第二主端子和第一主端子之间的输出电压（Vout）低于限定电平时，控制装置被布置用于减小控制端子和第一主端子之间的控制电压（Vcntr1）。

公开(公告)号：US06392490B1

公开(公告)日：2002-05-21

申请号：US09650022

申请日：2000-08-28

Applicant: Giuseppe Gramegna ,  Alessandro D'Aquila ,  B. Marco Marletta

Inventor： Giuseppe Gramegna ,  Alessandro D'Aquila ,  B. Marco Marletta

IPC: H03F122

CPC classification number: G05F3/205 ,  H03F1/223 ,  H03F1/301 ,  H03F3/45201 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/453 ,  H03F2203/45464 ,  H03F2203/45696 ,  H03F2203/45704

Abstract: A high-precision biasing circuit is provided for a CMOS cascode stage with inductive load and degeneration. The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The biasing circuit includes at least a first MOS replica transistor and a second MOS replica transistor, and two current generators for biasing the first and second MOS replica transistors. A circuit block detects a voltage value on a terminal of the second replica MOS transistor and applies a voltage to a gate terminal of the first replica transistor. Two circuit block implementations include a voltage amplifier and a folded cascode amplifier closed in a shunt feedback. Both implementations allow the threshold voltages of the cascode stage transistors to be tracked, as well as their Early and body effects.

Abstract translation: 为具有感性负载和退化的CMOS共源共栅级提供高精度偏置电路。 共射共栅级包括串联连接在第一参考电压和第二电压基准之间的至少两个MOS晶体管。 偏置电路至少包括第一MOS复制晶体管和第二MOS复制晶体管，以及用于偏置第一和第二MOS复制晶体管的两个电流发生器。 电路块检测第二复制MOS晶体管的端子上的电压值，并向第一复制晶体管的栅极端施加电压。 两个电路块实现包括在分流反馈中闭合的电压放大器和折叠共源共栅放大器。 这两种实现允许跟踪共源共栅级晶体管的阈值电压，以及它们的Early和body效应。