公开(公告)号：US07773010B2

公开(公告)日：2010-08-10

申请号：US12162814

申请日：2007-01-31

Applicant: Geert Van der Plas ,  Pierluigi Nuzzo ,  Fernando De Bernardinis

Inventor： Geert Van der Plas ,  Pierluigi Nuzzo ,  Fernando De Bernardinis

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/0607 ,  H03M1/0809 ,  H03M1/361

Abstract: The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.

Abstract translation: 本发明涉及包括至少两个电压比较器装置的模数（A / D）转换器。 每个电压比较器装置被布置成被馈送相同的输入信号并且用于产生自己的内部参考电压。 两个内部参考电压不同。 每个电压比较器被布置用于产生指示所述输入信号的数字近似的位位置的输出信号。

公开(公告)号：US07652600B2

公开(公告)日：2010-01-26

申请号：US12191059

申请日：2008-08-13

Applicant: Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

Inventor： Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/0809 ,  H03M1/0863 ,  H03M1/361

Abstract: The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.

Abstract translation: 本发明公开了一种包括至少两个电压比较器装置的模拟 - 数字转换器。 每个电压比较器装置包括晶体管的差分结构，并且被布置为被馈送相同的输入信号并且通过差分结构中的不平衡来产生自己的内部参考电压，所述两个内部电压基准是不同的。 每个电压比较器被布置用于产生指示输入信号的数字近似的位位置的输出信号。

公开(公告)号：US07501965B2

公开(公告)日：2009-03-10

申请号：US11755011

申请日：2007-05-30

Applicant: Seetharaman Janakiraman

Inventor： Seetharaman Janakiraman

IPC: H03M1/06

CPC classification number: H03M1/0809 ,  H03M1/38

Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.

Abstract translation: 导致产生的数字代码偏离预期值的模数转换器中的错误被更正。 模拟信号的样本被存储在存储元件中。 然后产生误差信号，其中误差信号表示模拟输入的样本的强度的预期数字代码与将被产生而不进行校正的值的偏差。 然后将误差信号添加到存储的样品。 在SAR ADC的上下文中实现的实施例中，基于部分数字码（样本的部分转换的结果）和误差系数来生成表示积分非线性误差的数字值。 数字值由辅助DAC转换为模拟形式，并添加到存储的输入采样。

公开(公告)号：US06633250B2

公开(公告)日：2003-10-14

申请号：US10108097

申请日：2002-03-27

Applicant: Chao-Cheng Lee ,  Pao-Cheng Chiu

Inventor： Chao-Cheng Lee ,  Pao-Cheng Chiu

IPC: H03M136

CPC classification number: H03M13/43 ,  H03M1/08 ,  H03M1/0809 ,  H03M1/36

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract translation: 本发明提供一种平均气泡校正电路，其将扩大气泡误差校正的范围，并且将检测温度计代码的1/0状态转换点的适当位置，以降低ROM引起的错误率 解码。 平均气泡校正电路用于模数转换器，并将从模数转换器的比较器获得的温度计代码转换为1/0状态转换点。

公开(公告)号：US06453309B1

公开(公告)日：2002-09-17

申请号：US09310640

申请日：1999-05-12

Applicant: Asko Kananen ,  Ari Paasio ,  Saska Lindfors ,  Kari Halonen

Inventor： Asko Kananen ,  Ari Paasio ,  Saska Lindfors ,  Kari Halonen

IPC: G06F9445

CPC classification number: H03M1/0809 ,  H03M1/365

Abstract: The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.

Abstract translation: 本发明涉及用于校正并行模数转换中的误差的方法和校正器​​（IC6）。 这种可校正误差是由转换器中的并行比较元件（IC1，IC2，IC3，IC4）的状态读数的不确定性引起的，所述不确定性是由诸如非同时状态锁存之类的非等级引起的。 使用非线性细胞神经网络来校正该误差，优选地，通过比较元件（IC1，IC2，IC3，IC4）比较元件（IC1，IC2，IC3，IC4）比较的现象的实际水平是通过估计与比较元件（IC1， ，IC2，IC3，IC4）在时间上或其他方式错误地读取。

公开(公告)号：US06396424B1

公开(公告)日：2002-05-28

申请号：US09574694

申请日：2000-05-17

Applicant: Hooman Reyhani ,  John Horan ,  John G. Ryan

Inventor： Hooman Reyhani ,  John Horan ,  John G. Ryan

IPC: H03M156

CPC classification number: H03M1/0809 ,  H03M1/361

Abstract: A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.

Abstract translation: 公开了一种气泡抑制装置，包括：第一组与门，其中第一组内的每个与门具有被配置为接收二进制温度计代码值和一个或多个相邻二进制温度计代码值的输入; 以及第二组与门，其中第二组中的每个与门具有耦合到第一组与门的两个或更多个输出的输入。

公开(公告)号：US06298459B1

公开(公告)日：2001-10-02

申请号：US09034219

申请日：1998-03-04

Applicant: Sanroku Tsukamoto

Inventor： Sanroku Tsukamoto

IPC: G06F1100

CPC classification number: H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

公开(公告)号：US6034630A

公开(公告)日：2000-03-07

申请号：US985273

申请日：1997-12-04

Applicant: Yoshihiro Komatsu ,  Kazuhisa Nojima

Inventor： Yoshihiro Komatsu ,  Kazuhisa Nojima

IPC: H03M1/36 ,  H03M1/08 ,  H03M7/16

CPC classification number: H03M1/0809 ,  H03M1/365

Abstract: An analog to digital converter, which, by comparing utput signals of a first comparator group with a reference voltage by a second comparator group and setting this reference voltage to a level lower than an intermediate level of output signals of the first comparator group, generation of the intermediate level signal in the output signals of the second comparator group is prevented, therefore a malfunction of the analog to digital converter can be avoided.

Abstract translation: 一种模数转换器，其通过将第一比较器组的输出信号与第二比较器组的参考电压进行比较，并将该参考电压设置为低于第一比较器组的输出信号的中间电平的电平， 可以防止第二比较器组的输出信号中的中间电平信号，因此可以避免模数转换器的故障。

公开(公告)号：US5272461A

公开(公告)日：1993-12-21

申请号：US929968

申请日：1992-08-14

Applicant: Bernhard Zojer

Inventor： Bernhard Zojer

IPC: H03M1/12 ,  H03M1/08 ,  H03M1/36 ,  H03M7/22

CPC classification number: H03M7/22 ,  H03M1/0809 ,  H03M1/36

Abstract: A coding circuit forming a 1-from-N code from an X-from-N code includes partial circuits in which each position of the X-from-N code forms an input value of a partial circuit. Each partial circuit is formed of three emitter-coupled transistor pairs, a current source connected to reference potential, level shift circuits, signal outputs and a symmetrical signal input. Each partial circuit is connected to the partial circuit with the next higher position of the X-from-N code as an input value and to the partial circuit with the next lower position of the X-from-N code as an input value.

Abstract translation: 从来自N-N码的从N代码构成的编码电路包括其中来自N代码的每个位置形成部分电路的输入值的部分电路。 每个部分电路由三个发射极耦合晶体管对，连接到参考电位的电流源，电平移位电路，信号输出和对称信号输入组成。 每个部分电路以X-N代码的下一较高位置作为输入值连接到部分电路，并将X-N代码的下一个较低位置作为输入值连接到部分电路。

公开(公告)号：US4983968A

公开(公告)日：1991-01-08

申请号：US418538

申请日：1989-10-10

Applicant: Truong-Thao Nguyen ,  Francois R. Thomas

Inventor： Truong-Thao Nguyen ,  Francois R. Thomas

IPC: H03M1/36 ,  H03M1/08

CPC classification number: H03M1/0809 ,  H03M1/36

Abstract: The disclosure pertains to parallel analog-digital converters, the first comparator stage of which give a so-called thermometer scale, formed by a sequence of logic "ones" and logic "zeros". According to the disclosure, a corrector stage is added on in series with the comparator stage. If a comparator of the first stage accidentally gives a logic value opposite that given by the two neighboring comparators, the corrector stages forces the accidentally erroneous value to assume the same value as that the values given by the two neighboring comparators, if and only if these values are equal. The disclosed device can be applied to signal processing ADCs.

Abstract translation: 本公开涉及并行模数转换器，其第一比较器级提供由逻辑“1”和逻辑“零”组成的所谓温度计量程。 根据本公开，与比较器级串联添加校正级。 如果第一级的比较器意外地给出与两个相邻比较器给出的逻辑值相反的逻辑值，则校正器级强制意外错误值与由两个相邻比较器给出的值相同，如果且仅当这些值 值相等。 所公开的器件可以应用于信号处理ADC。