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公开(公告)号：US07773010B2
公开(公告)日：2010-08-10
申请号：US12162814
申请日：2007-01-31
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/0607 , H03M1/0809 , H03M1/361
摘要： The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.
摘要翻译： 本发明涉及包括至少两个电压比较器装置的模数（A / D）转换器。 每个电压比较器装置被布置成被馈送相同的输入信号并且用于产生自己的内部参考电压。 两个内部参考电压不同。 每个电压比较器被布置用于产生指示所述输入信号的数字近似的位位置的输出信号。
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公开(公告)号：US08593170B2
公开(公告)日：2013-11-26
申请号：US12891658
申请日：2010-09-27
IPC分类号： G01R31/02 , G01R31/26 , G01R27/28 , H03K19/003 , H03K19/00
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译： 公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。 一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。 第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。 第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。 第一TSV和第二TSV之间的电连接在第二管芯的外部。 在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。
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公开(公告)号：US08094051B2
公开(公告)日：2012-01-10
申请号：US12776124
申请日：2010-05-07
IPC分类号： H03M3/00
摘要： An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal.
摘要翻译： 提出了一种用于产生RF模拟输入信号的数字输出信号的模数转换装置。 该器件包括第一模数转换器级，混频器，第二模数转换器级和数字滤波器。 第一模数转换器级产生第一和第二输出信号。 第一输出信号被输入到滤波装置中。 第二个输出信号被下变频为具有中频或DC的信号。 此后，该下变频信号被馈送到第二模数转换器级。 该第二级的数字输出信号与数字滤波器中的第一数字输出信号一起被进一步处理成表示模拟输入信号的数字信号。
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公开(公告)号：US20100283649A1
公开(公告)日：2010-11-11
申请号：US12776124
申请日：2010-05-07
IPC分类号： H03M3/00
摘要： An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal.
摘要翻译： 提出了一种用于产生RF模拟输入信号的数字输出信号的模数转换装置。 该器件包括第一模数转换器级，混频器，第二模数转换器级和数字滤波器。 第一模数转换器级产生第一和第二输出信号。 第一输出信号被输入到滤波装置中。 第二个输出信号被下变频为具有中频或DC的信号。 此后，该下变频信号被馈送到第二模数转换器级。 该第二级的数字输出信号与数字滤波器中的第一数字输出信号一起被进一步处理成表示模拟输入信号的数字信号。
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公开(公告)号：US08199043B2
公开(公告)日：2012-06-12
申请号：US12863149
申请日：2009-01-22
申请人： Geert Van der Plas , Bob Verbruggen
发明人： Geert Van der Plas , Bob Verbruggen
IPC分类号： H03M1/38
CPC分类号： H03M1/125 , H03M1/002 , H03M1/1235 , H03M1/361 , H03M1/42
摘要： An analog-to-digital converter that uses a comparator based asynchronous binary search is described. The architecture includes a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator only, for example to the first or root comparator. The at least one comparator is further arranged for controlling at least one other comparator of the plurality of comparators.
摘要翻译： 描述了使用基于比较器的异步二进制搜索的模数转换器。 该架构包括比较器的自定时（异步）分层二进制树，每个被布置成具有预定阈值。 输入信号与闪存转换器的情况并行地应用于所有比较器，但是时钟仅施加到（至少）一个比较器，例如到第一个或根比较器。 所述至少一个比较器还被布置用于控制所述多个比较器中的至少一个其它比较器。
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公开(公告)号：US20120025841A1
公开(公告)日：2012-02-02
申请号：US13194861
申请日：2011-07-29
申请人： Jaemin Kim , Geert Van der Plas , Paul Marchal
发明人： Jaemin Kim , Geert Van der Plas , Paul Marchal
IPC分类号： G01R31/02
CPC分类号： G01R27/2605 , G01R31/2853
摘要： A measurement system for determining the capacitance of a device-under-test in an integrated circuit is disclosed. In one aspect, the measurement system has a reference circuit and a test circuit. Each circuit has first and second diodes that are switched in accordance with a clock cycle to charge and discharge the associated circuit. A method takes average current measurements for each circuit at one voltage level and processes them so that the capacitance of a device-under-test connected to the test circuit can accurately and reliably be determined. Two voltage levels may be used and adjustments are made for voltage threshold of the diodes and also their resistance.
摘要翻译： 公开了一种用于确定集成电路中被测器件的电容的测量系统。 在一个方面，测量系统具有参考电路和测试电路。 每个电路具有根据时钟周期来切换以对相关电路进行充电和放电的第一和第二二极管。 一种方法在一个电压电平下对每个电路进行平均电流测量，并对它们进行处理，从而可以准确可靠地确定连接到测试电路的被测器件的电容。 可以使用两个电压电平，并且对二极管的电压阈值以及它们的电阻进行调整。
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公开(公告)号：US20110102011A1
公开(公告)日：2011-05-05
申请号：US12891658
申请日：2010-09-27
IPC分类号： G01R31/26 , H01L23/528
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31855 , H01L22/34 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
摘要翻译： 公开了一种用于在3D芯片堆栈中测试贯穿衬底通孔（TSV）的方法和装置。 一方面，3D芯片堆栈至少包括具有第一电路的第一管芯和具有第二电路的第二管芯。 第一模具还包括用于在第一电路和第二电路之间提供电连接的至少一个第一TSV。 第一裸片还包括测试电路和电连接在第一TSV和测试电路之间的至少一个第二TSV。 第一TSV和第二TSV之间的电连接在第二管芯的外部。 在一个方面，这允许测试第一裸片中的第一TSV，即使第二裸片没有设置专用测试电路。
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公开(公告)号：US20100328120A1
公开(公告)日：2010-12-30
申请号：US12863149
申请日：2009-01-22
申请人： Geert Van der Plas , Bob Verbruggen
发明人： Geert Van der Plas , Bob Verbruggen
CPC分类号： H03M1/125 , H03M1/002 , H03M1/1235 , H03M1/361 , H03M1/42
摘要： The present invention is related to an analog-to-digital converter circuit (1) wherein a comparator based asynchronous binary search is used. The architecture comprises a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator (2) only, preferably to the first or root comparator. The at least one comparator (2) is further arranged for controlling at least one other comparator (3) of the plurality of comparators (2, 3, 4).
摘要翻译： 本发明涉及一种使用基于比较器的异步二进制搜索的模数转换器电路（1）。 该架构包括比较器的自定时（异步）分层二进制树，每个布置为提供预定阈值。 输入信号与闪存转换器的情况一样并行地施加到所有比较器，但是时钟仅施加到（至少）一个比较器（2），优选地应用于第一或根比较器。 所述至少一个比较器（2）还被布置用于控制所述多个比较器（2,3,4）中的至少一个其它比较器（3）。
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公开(公告)号：US07652600B2
公开(公告)日：2010-01-26
申请号：US12191059
申请日：2008-08-13
申请人： Geert Van der Plas , Johan Bauwelinck , Zhisheng Li , Guy Torfs , Jan Vandewege , Xin Yin
发明人： Geert Van der Plas , Johan Bauwelinck , Zhisheng Li , Guy Torfs , Jan Vandewege , Xin Yin
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/0809 , H03M1/0863 , H03M1/361
摘要： The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.
摘要翻译： 本发明公开了一种包括至少两个电压比较器装置的模拟 - 数字转换器。 每个电压比较器装置包括晶体管的差分结构，并且被布置为被馈送相同的输入信号并且通过差分结构中的不平衡来产生自己的内部参考电压，所述两个内部电压基准是不同的。 每个电压比较器被布置用于产生指示输入信号的数字近似的位位置的输出信号。
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