公开(公告)号：US08453080B2

公开(公告)日：2013-05-28

申请号：US12335766

申请日：2008-12-16

申请人： Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

发明人： Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F7/62

CPC分类号： G06F17/5045

摘要： One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

摘要翻译： 一个或多个硬件描述语言（HDL）文件描述了定义要仿真的数字设计的多个分层布置的设计实体以及不属于数字设计的多个配置实体，所述多个配置实体逻辑地控制数字的多个配置锁存器的设置 设计。 编译HDL文件以获得数字设计的模拟可执行模型和相关联的配置数据库。 编译包括解析配置语句，该配置语句指定配置实体的实例与指定的配置锁存器之间的关联，确定在HDL文件中是否描述了指定的配置锁存器，以及如果不是，则创建指示 配置数据库，配置锁存器的实例与其无法绑定到的配置锁存器具有指定的关联。

公开(公告)号：US07885798B2

公开(公告)日：2011-02-08

申请号：US11746976

申请日：2007-05-10

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

IPC分类号： G06F17/50 ,  G06F7/62

CPC分类号： G06F17/5036

摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

摘要翻译： 一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。 第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。 在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。 模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

公开(公告)号：US07636612B2

公开(公告)日：2009-12-22

申请号：US11943078

申请日：2007-11-20

申请人： Elmar Weber ,  Hermann Benkler

发明人： Elmar Weber ,  Hermann Benkler

IPC分类号： G06F19/00 ,  G05B19/18 ,  G06F7/62 ,  G06F9/44

CPC分类号： B21D43/05 ,  G05B19/4069 ,  G05B2219/40317 ,  G05B2219/45142

摘要： A simulation method for optimizing transport displacement of workpieces in transfer presses is provided. Conclusions relating to the freedom of motion, number of strokes and program data for tool-specific machine control are determined by manipulating a displacement curve on a digital image of the transfer press which is determined by the simulation method.

摘要翻译： 提供了一种用于优化转印机中工件运输位移的模拟方法。 通过操作由模拟方法确定的转印机的数字图像上的位移曲线来确定与工具自由度，笔画数量和程序数据有关的结论。

公开(公告)号：US07464287B2

公开(公告)日：2008-12-09

申请号：US10815903

申请日：2004-03-31

申请人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

发明人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

IPC分类号： G06F5/06 ,  G06F17/50 ,  G06F7/62

CPC分类号： H04L49/9078 ,  H04L49/90

摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。

公开(公告)号：US07346479B2

公开(公告)日：2008-03-18

申请号：US09148392

申请日：1998-09-04

申请人： Franklin M. Baez

发明人： Franklin M. Baez

IPC分类号： G06F7/62

CPC分类号： G06F17/505

摘要： In one embodiment of the invention, parameter functions for a plurality of circuits in a subsystem are created. The subsystem has design constraints. Each one of the parameter functions corresponds to each one of the circuits. The parameter functions represent a relationship among design parameters of the subsystem. The design parameters include constraint and optimizing sets. Initial design points are selected on the parameter functions having a first sum of the constraint set and a second sum of the optimizing set such that the first sum satisfies the design constraints. New design points are selected on the parameter functions such that the second sum is improved within the design constraints.

摘要翻译： 在本发明的一个实施例中，创建子系统中多个电路的参数功能。 该子系统具有设计限制。 每个参数功能对应于每一个电路。 参数函数表示子系统的设计参数之间的关系。 设计参数包括约束和优化集。 在具有约束集合的第一和的优​​化集合的第一和的参数函数上选择初始设计点，使得第一和满足设计约束。 在参数功能上选择新的设计点，使得在设计约束内改进第二和。

公开(公告)号：US07020716B2

公开(公告)日：2006-03-28

申请号：US09944716

申请日：2001-08-31

申请人： Jignesh Raval ,  Purna Mohanty ,  Anil Kapatkar ,  Sivakumar Munnangi

发明人： Jignesh Raval ,  Purna Mohanty ,  Anil Kapatkar ,  Sivakumar Munnangi

IPC分类号： G06F15/153 ,  G06F7/62 ,  G06F9/455 ,  G06F17/50 ,  G01R31/08 ,  H04J1/16 ,  H04L12/26 ,  G06F15/16 ,  G06F13/12 ,  G06F9/44 ,  G06F11/00 ,  G08C15/00 ,  H04J3/14 ,  H04L1/00

CPC分类号： H04L69/163 ,  H04L43/50 ,  H04L69/16 ,  H04L69/161 ,  Y04S40/168

摘要： The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

公开(公告)号：US07013251B1

公开(公告)日：2006-03-14

申请号：US09461900

申请日：1999-12-15

申请人： Eric W. Nace ,  Adam C. Stone

发明人： Eric W. Nace ,  Adam C. Stone

IPC分类号： G06F17/50 ,  G06F7/62 ,  G06F13/10 ,  G06F13/12 ,  G06F15/173

CPC分类号： G06F11/3419 ,  G06F11/3476 ,  G06F11/3495 ,  G06F2201/875 ,  H04L41/069 ,  H04L41/145 ,  H04L43/028

摘要： A system and a method for server recording and client playback of computer network characteristics. In general, the network simulation system of the present invention includes a recording module that resides on a server and records and stores the network characteristics associated with networks sessions in a data collector file. The system also includes playback module that resides on a client receives the data collector file and plays back the data collector file upon request. The data collector file includes a log file, which is used to store initial request data, and a data file, which is used to store data other than the initial request data. The method of the present invention includes recording computer network characteristics on a recording server and playing back the recording on a client to the same or another server. The recording method of the present invention includes using a global filter residing on the server to record the network characteristics and storing the recording in a data collector file. The playback method includes receiving a data collector file containing recorded network characteristics recorded on a server and playing back the data collector file to simulate the characteristics of real-world network sessions.

摘要翻译： 一种用于服务器记录和客户端播放计算机网络特性的系统和方法。 通常，本发明的网络仿真系统包括驻留在服务器上的记录模块，并将与网络会话相关联的网络特性记录并存储在数据收集器文件中。 该系统还包括驻留在客户端上的播放模块接收数据收集器文件，并根据要求回放数据收集器文件。 数据收集器文件包括用于存储初始请求数据的日志文件和用于存储初始请求数据之外的数据的数据文件。 本发明的方法包括将计算机网络特性记录在记录服务器上并将客户端上的记录再现到相同或另一个服务器。 本发明的记录方法包括使用驻留在服务器上的全局过滤器来记录网络特性并将记录存储在数据收集器文件中。 回放方法包括接收包含记录在服务器上的记录的网络特征的数据收集器文件，并且回放数据收集器文件以模拟真实世界网络会话的特征。

公开(公告)号：US20050071036A1

公开(公告)日：2005-03-31

申请号：US10673501

申请日：2003-09-30

申请人： Andrej S. Mitrovic

发明人： Andrej S. Mitrovic

IPC分类号： G01R31/26 ,  G06F7/62 ,  G06F9/45 ,  G06F17/50 ,  H01L20060101 ,  H01L21/66 ,  G06F19/00

CPC分类号： G06F17/5018 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/80 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： A method, system and computer readable medium for facilitating a process performed by a semiconductor processing tool. The method includes inputting data relating to a process performed by the semiconductor processing tool, and inputting a first principles physical model relating to the semiconductor processing tool. First principles simulation is then performed using the input data and the physical model to provide a simulation result for the process performed by the semiconductor processing tool, and the simulation result is used as part of a data set that characterizes the process performed by the semiconductor processing tool.

摘要翻译： 一种用于促进由半导体处理工具执行的处理的方法，系统和计算机可读介质。 该方法包括输入与半导体处理工具执行的处理相关的数据，以及输入与半导体处理工具相关的第一原理物理模型。 然后使用输入数据和物理模型执行第一原理模拟，以提供由半导体处理工具执行的处理的仿真结果，并且将模拟结果用作表征由半导体处理执行的处理的数据集的一部分 工具。

公开(公告)号：US6127863A

公开(公告)日：2000-10-03

申请号：US282387

申请日：1999-03-31

申请人： Paul M. Elliott

发明人： Paul M. Elliott

IPC分类号： G06F7/62 ,  H03K21/00

CPC分类号： G06F7/62

摘要： In accordance with the invention, a method and structure are provided for obtaining a ratio of M/(2.sup.N +K) by feeding various carry-out (and/or complemented carry-out) signals from full-adders back to various frequency control inputs of the full-adders to modify the denominator of the division ratio. By doing this, K additional or fewer counts are accumulated during each cycle. Thus, the denominator can be changed from 2.sup.N to 2.sup.N +K, where K can be either positive or negative to obtain the desired M/(2.sup.N +K) ratio.

摘要翻译： 根据本发明，提供了一种方法和结构，用于通过将各种进位（和/或补码进位）信号从全加器馈送回各种频率控制输入来获得M /（2N + K）的比率 的全加法器来修改分母比的分母。 通过这样做，在每个周期内累积K个额外的或更少的计数。 因此，分母可以从2N改变为2N + K，其中K可以是正或负，以获得所需的M /（2N + K）比。

公开(公告)号：US6112217A

公开(公告)日：2000-08-29

申请号：US122056

申请日：1998-07-24

申请人： Peter Rohm ,  Patrick Leteinturier

发明人： Peter Rohm ,  Patrick Leteinturier

IPC分类号： G06F1/06 ,  G06F7/62 ,  G06F7/68 ,  G06F7/52

CPC分类号： G06F7/62 ,  G06F7/68

摘要： A method and an apparatus for generating clock signals is described, by which a period of time can be subdivided into a desired number of essentially equal-length segments. The method and the apparatus are distinguished in that the clock signals are generated based on the outcomes of a repeated subtraction of a first value from a second value. The first value depends on the number of segments into which the period of time to be subdivided is to be subdivided, and the second value depends on the duration of the period of time to be subdivided.

摘要翻译： 描述了用于产生时钟信号的方法和装置，通过该方法和装置可以将一段时间细分为期望数量的基本相等长度的段。 该方法和装置的区别在于，基于从第二值重复减去第一值的结果生成时钟信号。 第一个值取决于细分时间段的段数，第二个值取决于待细分的时间段的持续时间。