利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

1065 records (took 0.022 seconds)

    Inverter circuit
    71.
    发明授权
    Inverter circuit 失效
    逆变电路

    公开(公告)号：US4999517A

    公开(公告)日：1991-03-12

    申请号：US433472

    申请日：1989-11-08

    Applicant: Toru Yamazaki

    Inventor： Toru Yamazaki

    IPC: H03K17/567 ,  H03K19/017 ,  H03K19/08 ,  H03K19/0944

    CPC classification number: H03K19/09448 ,  H03K19/01707

    Abstract: An inverter circuit comprises a bipolar transistor having a collector and an emitter of a first conductivity type, and at least three field effect transistors of which the first one includes a channel of a second conductivity type, the second one includes a channel of the first conductivity type, and the third one includes a channel of the first conductivity type. The first field effect transistor with the channel of the second conductivity type is connected at the gate thereof to ground to be permanently turned on. As a result, the first field effect transistor is used as a load. The inverter circuit provides the reduction in the number of transistors typically used therein and decrease in an input capacitance, even if a multi-gate input structure is adopted.

    Abstract translation: 逆变器电路包括具有第一导电类型的集电极和发射极的双极晶体管，以及至少三个场效应晶体管，其中第一导体类型的沟道具有第二导电类型的沟道，第二场效应晶体管包括第一导电类型的沟道 类型，并且第三个包括第一导电类型的通道。 具有第二导电类型的沟道的第一场效应晶体管在其栅极处连接到地，以永久地导通。 结果，第一场效应晶体管被用作负载。 即使采用多栅极输入结构，逆变器电路也减少了通常在其中使用的晶体管的数量并降低了输入电容。

    Bi-CMOS logic circuit
    72.
    发明授权
    Bi-CMOS logic circuit 失效
    双CMOS逻辑电路

    公开(公告)号：US4977337A

    公开(公告)日：1990-12-11

    申请号：US462378

    申请日：1990-01-09

    Applicant: Shigeki Ohbayashi ,  Katsushi Asahina

    Inventor： Shigeki Ohbayashi ,  Katsushi Asahina

    IPC: H03K17/567 ,  H03K19/00 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

    CPC classification number: H03K19/001 ,  H03K19/0136 ,  H03K19/09448

    Abstract: A Bi-CMOS logic circuit structured by bipolar transistors and insulated gate type transistors includes a first NPN bipolar transistor for charging an output node and a second NPN bipolar transistor for discharging the output node. The first bipolar transistor has a collector coupled to a first power supply and an emitter connected to the output node. The second bipolar transistor has a collector connected to the output node and an emitter coupled to a second power supply. The Bi-CMOS logic circuit also includes at least one P channel insulated gate type transistor provided between the first power supply and a base of the first bipolar transistor for receiving an input signal at its gate, and at least one N channel insulated gate type transistor provided between the output node and a base of the second bipolar transistor for receiving the input signal at its gate. The Bi-CMOS logic circuit further includes a third NPN bipolar transistor for drawing charges out of the base of the first bipolar transistor, and an impedance element for biasing the base of the second bipolar transistor relative to the second power supply. The third bipolar transistor has a collector connected to the base of the first bipolar transistor, a base connected to the base of the second bipolar transistor and an emitter connected to the second power supply. The impedance element includes a fourth N channel insulated gate type transistor having a gate connected to the output node, one conduction terminal connected to the respective bases of the second and third bipolar transistors, and other conduction terminal coupled to the second power supply.

    Abstract translation: 由双极晶体管和绝缘栅型晶体管构成的Bi-CMOS逻辑电路包括用于对输出节点充电的第一NPN双极晶体管和用于对输出节点放电的第二NPN双极晶体管。 第一双极晶体管具有耦合到第一电源的集电极和连接到输出节点的发射极。 第二双极晶体管具有连接到输出节点的集电极和耦合到第二电源的发射极。 Bi-CMOS逻辑电路还包括设置在第一电源和第一双极晶体管的基极之间的至少一个P沟道绝缘栅型晶体管，用于在其栅极处接收输入信号，以及至少一个N沟道绝缘栅型晶体管 设置在输出节点和第二双极晶体管的基极之间，用于在其栅极处接收输入信号。 Bi-CMOS逻辑电路还包括用于从第一双极晶体管的基极吸取电荷的第三NPN双极晶体管，以及用于相对于第二电源偏置第二双极晶体管的基极的阻抗元件。 第三双极晶体管具有连接到第一双极晶体管的基极的集电极，连接到第二双极晶体管的基极的基极和连接到第二电源的发射极。 阻抗元件包括具有连接到输出节点的栅极的第四N沟道绝缘栅型晶体管，连接到第二和第三双极晶体管的相应基极的一个导通端子和耦合到第二电源的其它导通端子。

    CMOS to ECL output buffer
    73.
    发明授权
    CMOS to ECL output buffer 失效
    CMOS到ECL输出缓冲器

    公开(公告)号：US4912347A

    公开(公告)日：1990-03-27

    申请号：US089284

    申请日：1987-08-25

    Applicant: Bernard L. Morris

    Inventor： Bernard L. Morris

    IPC: H03K19/00 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/0948

    CPC classification number: H03K19/09448 ,  H03K19/0136 ,  H03K19/017518

    Abstract: A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical "zero" logic signal. The current from the current source passing through the resistor establishes the ECL logical "zero" output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical "one" output, allowing faster transitioning of the output of the buffer from an ECL logical "zero" to a logical "one". Further, the current from the current source compensates for variations in the resistance of the resistor to assure a substantially constant difference between the ECL logical "one" and the ECL logical "zero" output voltages with variations in the resistance of the resistor from the manufacture thereof.

    Logic circuit used in standard IC or CMOS logic level
    74.
    发明授权
    Logic circuit used in standard IC or CMOS logic level 失效
    逻辑电路用于标准IC或CMOS逻辑电平

    公开(公告)号：US4902914A

    公开(公告)日：1990-02-20

    申请号：US154066

    申请日：1988-02-09

    Applicant: Hideaki Masuoka

    Inventor： Hideaki Masuoka

    IPC: H01L21/8249 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H03K19/00 ,  H03K19/08 ,  H03K19/0944

    CPC classification number: H03K19/0013 ,  H03K19/09448

    Abstract: A logic circuit includes first and second NPN bipolar transistors whose collector-emitter paths are serially connected between a power source potential terminal and a ground terminal, the connection node of the first and second bipolar transistors being connected to a signal input terminal; a first CMOS logic circuit having an input terminal connected to a signal input terminal and an output terminal connected to the base of the first NPN bipolar transistor; a second CMOS logic circuit having an input terminal connected to the signal input terminal and an output terminal connected to the signal output terminal; a first switching circuit connected between the signal output terminal and the base of the second bipolar transistor, and to be set OFF when an input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive; and a second switching circuit connected between the second potential supply source and the base of the second NPN bipolar transistor, and to be set OFF when the input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive.

    Current mirror switching circuit
    75.
    发明授权
    Current mirror switching circuit 失效
    电流镜开关电路

    公开(公告)号：US4883988A

    公开(公告)日：1989-11-28

    申请号：US262290

    申请日：1988-10-25

    Applicant: Akira Ide ,  Yoshikazu Saito

    Inventor： Akira Ide ,  Yoshikazu Saito

    IPC: H03K19/08 ,  G11C11/408 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/0948

    CPC classification number: H03K19/017527 ,  H03K19/018514 ,  H03K19/09448 ,  H03K19/0948

    Abstract: A level conversion circuit having a plurality of switching elements connected in series or in parallel to a part thereof and having inputted a plurality of complementary signals to the plurality of switching elements connected in series or in parallel, and a high speed and high driving power switching circuit having a bipolar transistor which is directly driven by an output of such level conversion circuit and which provides level conversion and logic functions.

    Abstract translation: 一种电平转换电路，具有与其一部分串联或并联连接的多个开关元件，并且对串联或并联连接的多个开关元件输入多个互补信号，以及高速和高驱动功率开关 电路具有由这种电平转换电路的输出直接驱动并提供电平转换和逻辑功能的双极晶体管。

    Bipolar transistor and CMOS transistor logic circuit having improved discharge capabilities
    76.
    发明授权
    Bipolar transistor and CMOS transistor logic circuit having improved discharge capabilities 失效
    具有改善的放电能力的双极晶体管和CMOS晶体管逻辑电路

    公开(公告)号：US4880998A

    公开(公告)日：1989-11-14

    申请号：US179299

    申请日：1988-04-08

    Applicant: Masahiro Ueda

    Inventor： Masahiro Ueda

    IPC: H03K17/04 ,  H01L21/8249 ,  H01L27/06 ,  H03K17/12 ,  H03K17/567 ,  H03K19/01 ,  H03K19/017 ,  H03K19/08 ,  H03K19/0944

    CPC classification number: H03K19/01721 ,  H03K19/09448

    Abstract: The present invention provides a logic circuit which is formed by combination of bipolar transistors and CMOS transistors such that conduction of the bipolar transistors is controlled by the MOS transistors and an output load is charged/discharged by the conducting bipolar transistors. A logic part formed by combination of at least one or more NMOS transistors is provided between an output terminal and a low-potential power source, so that fall of output voltage in discharging is prompted by addition of discharge path through the logic part.

    Abstract translation: 本发明提供了一种通过双极晶体管和CMOS晶体管的组合形成的逻辑电路，使得双极晶体管的导通由MOS晶体管控制，并且由导电双极晶体管对输出负载进行充电/放电。 在输出端子和低电位电源之间提供由至少一个或多个NMOS晶体管组合形成的逻辑部分，从而通过添加通过逻辑部分的放电路径来促进放电中的输出电压的下降。

Patent Agency Ranking