公开(公告)号：US20120106286A1

公开(公告)日：2012-05-03

申请号：US12912971

申请日：2010-10-27

Applicant: Cheng Hung LEE ,  Hsu-Shun CHEN

Inventor： Cheng Hung LEE ,  Hsu-Shun CHEN

IPC: G11C8/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/10 ,  G11C11/418

Abstract: The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.

Abstract translation: 本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器， 耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。 存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

公开(公告)号：US20110242904A1

公开(公告)日：2011-10-06

申请号：US12983985

申请日：2011-01-04

Applicant: Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

Inventor： Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

IPC: G11C16/08

CPC classification number: G11C8/08 ,  G11C17/14

Abstract: A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.

Abstract translation: 提供只读存储器（ROM）及其操作方法。 只读存储器包括：控制电路，由第一电源供电，用于在第一电压范围内输出控制信号; 电压移位器，用于将控制信号的振幅扩大到第二电压范围; 由具有比第一电源的电压高的第二电源供电的字线驱动器，用于根据扩展至的只读存储单元阵列的多个字线中的一个字线驱动 处于第二电压范围内; 以及用于连接多个位线以读出消息的输入/输出电路。

公开(公告)号：US20110188326A1

公开(公告)日：2011-08-04

申请号：US12700034

申请日：2010-02-04

Applicant: Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Lu

Inventor： Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Lu

IPC: G11C7/00 ,  G11C8/08

CPC classification number: G11C7/00 ,  G11C8/08

Abstract: A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.

Abstract translation: 静态随机存取存储器（SRAM）宏包括与第一电源电压不同的第一电源电压和第二电源电压。 预充电控制连接到第二电源电压。 预充电控制通过位线预充电耦合到位线。 至少一个电平移位器接收电平移位器输入。 电平移位器将具有比第二电源电压更接近于第一电源电压的电压电平的电平移位器输入转换为具有比第一电源电压更接近第二电源电压的电压电平的电平移位器输出。 电平移位器输出被提供给预充电控制。

公开(公告)号：US07913215B2

公开(公告)日：2011-03-22

申请号：US11493405

申请日：2006-07-26

Applicant: Chung-Cheng Chou ,  Cheng-Hung Lee

Inventor： Chung-Cheng Chou ,  Cheng-Hung Lee

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.

Abstract translation: 存储器宏包括设置在存储器阵列的第一区域中的第一组单元，以及设置在第一区域的边缘处的与物理尺寸的第一组单元不同的第二组单元，用于改善第一区域的鲁棒性 存储器阵列边缘的单元格。

公开(公告)号：US20100259999A1

公开(公告)日：2010-10-14

申请号：US12754733

申请日：2010-04-06

Applicant: Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

IPC: G11C7/00 ,  H03L5/00

CPC classification number: H01L27/1104 ,  G11C11/419

Abstract: A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

Abstract translation: 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US20100254209A1

公开(公告)日：2010-10-07

申请号：US12694032

申请日：2010-01-26

Applicant: Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C5/063

Abstract: An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.

Abstract translation: 集成电路结构包括有源电源线和数据保持电源线。 存储器宏连接到有源电源线和数据保持电源线。 存储器宏包括存储单元阵列和开关。 该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。 数据保持电源线在存储器宏之外。

公开(公告)号：US07750375B2

公开(公告)日：2010-07-06

申请号：US11529925

申请日：2006-09-30

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.

Abstract translation: 本发明公开了一种具有多个模块单元的集成电路（IC）芯片，该芯片包括具有第一金属层的第一模块单元，该第一金属层包含彼此独立的至少两条电源线; 以及与第一模块单元并置的第二模块单元，其还具有第一金属层，该第一金属层包含彼此独立的至少两个电力线，其中用于第一模块单元的第一金属层上的所有电力线不延伸 并且服务于第二模块的第一金属层上的所有电力线不延伸到第一模块单元中。

公开(公告)号：US07613057B2

公开(公告)日：2009-11-03

申请号：US11732297

申请日：2007-04-03

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C5/025

Abstract: A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.

Abstract translation: 一种电路和方法，用于为控制信号中的失真提供用于DRAM存储器的读出放大器，该读出放大器特别适用于将具有其他逻辑和存储器功能的DRAM存储器嵌入集成电路中。 为具有级联耦合的晶体管对的读出放大器中的差分感测锁存器提供感测使能电路，每个晶体管接收单独的控制信号。 单独的控制信号由具有延迟重叠的控制电路提供。 当分离的控制信号之间存在延迟的重叠时，启用差分感测。 DRAM存储单元的阵列耦合到多个读出放大器。 结合读出放大器的DRAM存储器可以与集成电路中的其它电路嵌入。 提供了提供控制信号和用读出放大器布置DRAM存储器的方法。

公开(公告)号：US20080229161A1

公开(公告)日：2008-09-18

申请号：US11686996

申请日：2007-03-16

Applicant: Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C29/70 ,  G11C29/80 ,  G11C2029/5004 ,  H01L22/22 ,  H01L27/1052

Abstract: Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.

Abstract translation: 内存产品及其制造方法。 存储器产品包括至少一个存储器单元和至少一个冗余存储单元。 存储单元和冗余存储单元具有不同的物理或电子特性。 如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

公开(公告)号：US20080080123A1

公开(公告)日：2008-04-03

申请号：US11529925

申请日：2006-09-30

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01G9/00

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.

Abstract translation: 本发明公开了一种具有多个模块单元的集成电路（IC）芯片，该芯片包括具有第一金属层的第一模块单元，该第一金属层包含彼此独立的至少两条电源线; 以及与第一模块单元并置的第二模块单元，其还具有第一金属层，该第一金属层包含彼此独立的至少两个电力线，其中用于第一模块单元的第一金属层上的所有电力线不延伸 并且服务于第二模块的第一金属层上的所有电力线不延伸到第一模块单元中。