公开(公告)号：US20100259999A1

公开(公告)日：2010-10-14

申请号：US12754733

申请日：2010-04-06

Applicant: Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

IPC: G11C7/00 ,  H03L5/00

CPC classification number: H01L27/1104 ,  G11C11/419

Abstract: A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

Abstract translation: 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US20130010560A1

公开(公告)日：2013-01-10

申请号：US13535075

申请日：2012-06-27

Applicant: Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

Inventor： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

IPC: H03F3/45 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

Abstract translation: 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

公开(公告)号：US20130003445A1

公开(公告)日：2013-01-03

申请号：US13609930

申请日：2012-09-11

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/40 ,  H01L21/8244

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US20110063894A1

公开(公告)日：2011-03-17

申请号：US12877695

申请日：2010-09-08

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/00 ,  H01R43/00

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US20130258747A1

公开(公告)日：2013-10-03

申请号：US13437081

申请日：2012-04-02

Applicant: Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

IPC: G11C17/00 ,  G11C11/00 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

公开(公告)号：US20120206953A1

公开(公告)日：2012-08-16

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C5/06 ,  H01L25/00

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US20120014158A1

公开(公告)日：2012-01-19

申请号：US12838572

申请日：2010-07-19

Applicant: Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

Inventor： Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

IPC: G11C17/12

CPC classification number: G11C17/12

Abstract: A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time.

Abstract translation: 存储器件包括晶体管阵列，多个位线和多条源极线。 晶体管包括栅极，漏极和源极端子。 栅极端子电耦合到字线。 多个位线将电源连接到晶体管阵列的漏极端子，并且多个源极线将电源连接到晶体管阵列的源极端子。 在待机模式期间，这些连接被激活，从而限制泄漏电流，而不会引起与存储器访问/周期时间下降有关的缺点。

公开(公告)号：US20140269110A1

公开(公告)日：2014-09-18

申请号：US13837614

申请日：2013-03-15

Applicant: Jung-Ping YANG ,  Chia-En HUANG ,  Fu-An WU ,  Chih-Chieh CHIU ,  Cheng Hung LEE

Inventor： Jung-Ping YANG ,  Chia-En HUANG ,  Fu-An WU ,  Chih-Chieh CHIU ,  Cheng Hung LEE

IPC: G11C7/06 ,  G06F17/50

CPC classification number: G11C7/065 ,  G06F17/5063 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/419

Abstract: A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.

Abstract translation: 用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。 存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。 第一和第二节点分别耦合到第一和第二位线。 输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流 响应于从存储器单元读出的第二数据的电压。 输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。 第一个电流大于第二个电流。

公开(公告)号：US20130208533A1

公开(公告)日：2013-08-15

申请号：US13372099

申请日：2012-02-13

Applicant: Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

Inventor： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

IPC: G11C11/40 ,  G11C7/12 ,  G11C7/00

CPC classification number: G11C11/4094 ,  G11C11/419

Abstract: A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

Abstract translation: 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US20130194877A1

公开(公告)日：2013-08-01

申请号：US13362847

申请日：2012-01-31

Applicant: Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

Inventor： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/18 ,  G11C11/419 ,  G11C2207/005

Abstract: A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.

Abstract translation: 存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。 每个存储块包括一对位线和耦合到该对位线的多个存储器单元。 每个全局位线耦合到至少一个存储器块。 预充电电路被配置为将全局位线一次一个地预充电到预充电电压。 选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。