摘要:
The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
摘要:
A Dual Gate BCMD pixel has a compact size, nondestructive readout; complete reset with no kTC-reset noise generation, anti-blooming protection, and column reset capability. By incorporating a dual gate MOS transistor with an enclosed annular layout into the pixels of image sensing array, and sensing photo-generated charge nondestructively by detecting the transistor threshold voltage variations caused by collected charge, achieves this goal and other objects of the invention.
摘要:
The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication register consists of multi-channel sections that are evenly positioned around the periphery of the image sensing area. The individual charge multiplying register sections are coupled together by only 90-degree multi-channel turns located at the image area array corners. The device allows for the optical image sensing area center to be located near the chip center and consequently near the mechanical package center with the minimum silicon chip area sacrifice.
摘要:
Image sensors with an enhanced QE and MTF in the NIR spectral region are fabricated on the standard substrates. This is achieved by replacing the p+ type doped layer, typically present under the thick field oxide in the inactive regions of the sensor, with an n+ type doped layer. The n+ type layer, which is biased at the Vdd potential, surrounds the entire image sensor array as a guard ring and is separated from the CCD or CMOS array pixels by a suitable potential barrier. The potential barrier prevents collected charge from escaping into the n+ layer regions. Additional embodiments include output diode and MOS transistor designs that use field plates for creating potential barriers that separate these devices from the n+ type doped field regions.
摘要:
A new High Dynamic Range charge detection concept useful for CCD and Active Pixel CMOS image sensors uses at least one transistor operating in a punch through mode for the charge detection node reset. The punch through operation significantly reduces the reset feed through which leads to a higher voltage swing available on the node for the signal. This in turn allows building smaller and thus more sensitive charge detection nodes. The undesirabe artifacts, associated with the incomplete reset that are induced by the punch through operation, are completely removed by incorporating the CDS signal processing method into the signal processing chain. The incomplete reset artifact removal by the CDS technique is extended to all other resetting concepts that are modeled by a large reset time constant. The punch through concept is suitable for resetting Floating Diffusion charge detection nodes as well as Floating Gate charge detection nodes.
摘要:
An image sensing device includes: a light sensing element 20 for providing a signal in response to incident light; a comparator 24 coupled to the photo sensing element 20 for detecting when the signal reaches a reference level VREF; a resetting device 22 coupled to the light sensing element 20 for resetting the light sensing element 20 when the signal reaches the reference level VREF; and a memory device 26 coupled to the comparator 24 for receiving and storing an output from the comparator 24.
摘要:
A bulk charge modulated MOSFET for sensing light comprising a semiconductor substrate with a gate region of a first conductivity type formed in the substrate. The gate region forms a potential well for carriers of the first conductivity type. The well is formed at a substantial depth from the surface of the gate region. The carriers are formed responsive to incident light. The gate region collects the carriers generated at depths less than the well. A source region of a second conductivity type is formed in the semiconductor substrate laterally adjacent the gate region. The source region is operable to sense a change in threshold voltage of the MOSFET responsive to the collection of carriers by the gate region. A drain region of the second conductivity type is formed in the layer adjacent the gate region and spaced from the source. The drain region is connected to a voltage source. The voltage source is pulsed to create a large potential well that extends under the gate region from the source to the drain during charge integration period and a smaller potential well during readout period.
摘要:
For a buffer amplifier provided near a solid state imaging device for photoelectrically converting an optical image by an image forming optical system and amplifying the signal of the output end, the temperature rise of the solid state imaging device is reduced by reducing the electric power consumption in a non-signal reading out period in which no driving signal is applied against a signal reading out period in which an image signal is output from the output end of this solid state imaging device by applying a driving signal to the solid state imaging device.
摘要:
Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.
摘要翻译:描述了一种新的高性能CCD图像传感器技术,可用于构建具有高分辨率和高像素密度的传感器的通用图像传感器系列。 所描述的传感器架构基于新的充电超扫描概念,其被开发用于克服诸如开花和图像涂片的常见问题。 电荷超扫描发生在位于类似于Interline Transfer CCD器件的光电子之间的非常窄的垂直通道中。 这里的区别在于,在任何相当长的时间内,电荷从不存储在这些区域中,并且使用新的电阻栅极行波扫描技术扫除。 电荷超扫描方法还允许在单个水平消隐间隔期间将位于阵列中任何位置的光子的几行数据快速电荷传输到缓冲存储器中。
摘要:
A bulk charge modulated transistor threshold sensing element (12) comprises a first region (18) having an enclosed structure, a gate region (24) that is preferably generally endless in shape, and a second region (26) to the interior of the gate region (24). The gate region (24) is doped and biased such that a potential well (100) is formed in the semiconductor substrate (11) a substantial distance from the surface thereof. When light (90) impinges on the element of the invention, carriers (94) collect in the potential well (100) in response thereto. The carriers (94) affect the threshold voltage of the transistor sensor element, and a threshold voltage differential is sensed as the sensing signal.