Systems and methods for monitoring copper corrosion in an integrated circuit device

    公开(公告)号:US11573189B2

    公开(公告)日:2023-02-07

    申请号:US16683987

    申请日:2019-11-14

    Inventor: Yaojian Leng

    Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

    ADJUSTABLE LIGHT SOURCE
    82.
    发明申请

    公开(公告)号:US20230028136A1

    公开(公告)日:2023-01-26

    申请号:US17649884

    申请日:2022-02-03

    Abstract: Various examples relate to adjustable light sources. An example may include an apparatus including a light source to adjustably emit light toward a region of interest at least partially responsive to a control signal. The apparatus may also include a sensor to generate a signal indicative of an intensity of light sensed by the sensor in the region of interest. The apparatus may also include a wireless-communication equipment to broadcast a value that represents the intensity of light received by the sensor. The wireless-communication equipment may also receive a broadcast of a further value that represents an intensity of light in a further region of interest. The apparatus may also include a processor to adjust the control signal at least partially responsive to the further value. Related devices, systems and methods are also disclosed.

    Three-dimensional metal-insulator-metal (MIM) capacitor

    公开(公告)号:US11545544B2

    公开(公告)日:2023-01-03

    申请号:US17155431

    申请日:2021-01-22

    Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

    Metal-insulator-metal (MIM) capacitor

    公开(公告)号:US11545428B2

    公开(公告)日:2023-01-03

    申请号:US16999358

    申请日:2020-08-21

    Inventor: Yaojian Leng

    Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

    Thin film resistor (TFR) formed in an integrated circuit device using TFR cap layer(s) as an etch stop and/or hardmask

    公开(公告)号:US11508500B2

    公开(公告)日:2022-11-22

    申请号:US17071442

    申请日:2020-10-15

    Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.

    Daisy chain streaming mode
    88.
    发明授权

    公开(公告)号:US11494324B2

    公开(公告)日:2022-11-08

    申请号:US16998097

    申请日:2020-08-20

    Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.

    Memory pool allocation for a multi-core system

    公开(公告)号:US11461139B2

    公开(公告)日:2022-10-04

    申请号:US16842870

    申请日:2020-04-08

    Abstract: An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.

    SENSE COIL FOR INDUCTIVE ROTATIONAL-POSITION SENSING, AND RELATED DEVICES, SYSTEMS, AND METHODS

    公开(公告)号:US20220307868A1

    公开(公告)日:2022-09-29

    申请号:US17303675

    申请日:2021-06-04

    Abstract: An apparatus for inductive rotational-position sensing is disclosed. An apparatus may include an electrically conductive material defining a continuous path for electrical current to flow between a first and a second location. The continuous path may include a first path portion, defined as a generally clockwise path for the electrical current to flow around a geometric center of the continuous path, and a second path portion, defined as a generally counter-clockwise path for the electrical current to flow around the geometric center. The continuous path may also include a radial-direction-reversal region at which one of the first path portion or the second path portion changes from being defined as a generally outward path for the electrical current to flow away from the geometric center to being defined as a generally inward path for the electrical current to flow toward the geometric center. Related systems, devices, and methods are also disclosed.

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