公开(公告)号：US20230006753A1

公开(公告)日：2023-01-05

申请号：US17745143

申请日：2022-05-16

Applicant: Microchip Technology Inc.

Inventor： Steven Scott GORSHE ,  Winston Mok

IPC: H04J3/16 ,  H04J3/07

Abstract: A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a variable number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.

公开(公告)号：US20220383970A1

公开(公告)日：2022-12-01

申请号：US17506735

申请日：2021-10-21

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G11C29/02 ,  G11C29/44 ,  G11C29/10 ,  G11C29/50 ,  G11C11/54

Abstract: A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

公开(公告)号：US20220382945A1

公开(公告)日：2022-12-01

申请号：US17740644

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Gabriel Barajas ,  Fei Li ,  Hassan Hassan ,  James Sumit Tandon

IPC: G06F30/347

Abstract: A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.

公开(公告)号：US20220375532A1

公开(公告)日：2022-11-24

申请号：US17385857

申请日：2021-07-26

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06N3/063 ,  G06N3/08

Abstract: A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

公开(公告)号：US20220294439A1

公开(公告)日：2022-09-15

申请号：US17548988

申请日：2021-12-13

Applicant: Microchip Technology Inc.

Inventor： Tamir LANGER ,  Migel Jacubovski

IPC: H03K17/082 ,  G01K7/01 ,  H02H5/04

Abstract: A method (50, 70, 600) provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed (51), each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled (52) to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated (53) over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared (54) to a threshold value. An action related to the thermal protection function is initiated (55) upon the integration output of an affected component exceeding the threshold value.

公开(公告)号：US20220191144A1

公开(公告)日：2022-06-16

申请号：US17383755

申请日：2021-07-23

Applicant: Microchip Technology Inc.

Inventor： Morten Terstrup

IPC: H04L12/851 ,  H04L12/841 ,  H04L12/863 ,  H04L12/935 ,  H04L12/743

Abstract: A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.

公开(公告)号：US11341304B2

公开(公告)日：2022-05-24

申请号：US17111218

申请日：2020-12-03

Applicant: Microchip Technology Inc.

Inventor： Madhusudan Raman ,  Nizar Abdallah ,  Julien G. Dunoyer

IPC: G06F30/343 ,  G06F119/12 ,  G06N3/08

Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

公开(公告)号：US11271712B2

公开(公告)日：2022-03-08

申请号：US16827624

申请日：2020-03-23

Applicant: Microchip Technology Inc.

Inventor： Thomas Joergensen ,  Brian Branscomb

IPC: H04L7/00 ,  H04L12/931 ,  H04L49/351

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

公开(公告)号：US20220027083A1

公开(公告)日：2022-01-27

申请号：US17089891

申请日：2020-11-05

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06F3/06 ,  G06N3/04 ,  G06N5/04

Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

公开(公告)号：US11222782B2

公开(公告)日：2022-01-11

申请号：US16785491

申请日：2020-02-07

Applicant: Microchip Technology Inc.

Inventor： Amaury Gendron-Hansen ,  Bruce Odekirk

IPC: H01L21/02 ,  H01L21/04 ,  H01L27/092 ,  H01L21/67

Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.