公开(公告)号：US20170146666A1

公开(公告)日：2017-05-25

申请号：US15136211

申请日：2016-04-22

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Stephane Dorbes

IPC: G01S19/35 ,  G01S19/24

CPC classification number: G01S19/35 ,  G01S19/24 ,  G01S19/32 ,  G01S19/33 ,  G01S19/36

Abstract: The receiver for a satellite positioning system includes at least one receive channel with an input stage configured to receive a satellite signals having different constellation frequencies belonging to one frequency band or to different frequency bands. The receive channel further includes a frequency transposition stage connected to the input stage (EE) and including a controllable local oscillator device configured to deliver different frequency transposition signals respectively adapted to the different constellation frequencies. A processing stage of the receive channel is connected to the frequency transposition stage and includes a control circuit configured to control the local oscillator device to sequentially and cyclically deliver the different frequency transposition signals.

公开(公告)号：US12141590B2

公开(公告)日：2024-11-12

申请号：US17898306

申请日：2022-08-29

Applicant: STMicroelectronics France ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Frederic Ruelle ,  Emmanuel Grandin ,  Bechir Jabri

IPC: G06F9/445 ,  G06F3/0482 ,  G06F9/4401 ,  G06F9/451

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

公开(公告)号：US12045175B2

公开(公告)日：2024-07-23

申请号：US17457569

申请日：2021-12-03

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Frederic Ruelle

IPC: G06F12/14 ,  G06F21/54 ,  G06F21/55 ,  G06F21/78

CPC classification number: G06F12/1441 ,  G06F12/1458 ,  G06F21/54 ,  G06F21/556 ,  G06F21/78

Abstract: A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.

公开(公告)号：US20240176689A1

公开(公告)日：2024-05-30

申请号：US18514812

申请日：2023-11-20

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0745

Abstract: The system-on-chip includes at least one master device, at least one slave resource, an interconnection bus including an error notification channel, and a resource isolation system including, for each resource, a protection circuit configured to block or transmit transactions addressed to the resource via the interconnection bus, according to access rights of the resource and the transaction. The protection circuit is capable of generating a notification signal on the error notification channel of the interconnection bus in case of blockage of a transaction.

公开(公告)号：US11962462B2

公开(公告)日：2024-04-16

申请号：US18321516

申请日：2023-05-22

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Nicolas Anquet ,  Loic Pallardy

IPC: H04L41/0803 ,  G06F15/173 ,  G06F15/177 ,  H04L41/0813 ,  H04L49/109 ,  G06F21/85

CPC classification number: H04L41/0813 ,  G06F15/17306 ,  G06F15/177 ,  H04L41/0803 ,  H04L49/109 ,  G06F21/85

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

公开(公告)号：US20240067184A1

公开(公告)日：2024-02-29

申请号：US18496124

申请日：2023-10-27

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS, INC. ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Nicola Matteo PALELLA ,  Leonardo COLOMBO ,  Andrea DONADEL ,  Roberto MURA ,  Mahaveer JAIN ,  Joelle PHILIPPE

IPC: B60W40/101 ,  B60W40/11 ,  B60W40/112 ,  B60W40/114 ,  G01S19/47

CPC classification number: B60W40/101 ,  B60W40/11 ,  B60W40/112 ,  B60W40/114 ,  G01S19/47 ,  B60W2520/28

Abstract: A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.

公开(公告)号：US11893370B2

公开(公告)日：2024-02-06

申请号：US17451394

申请日：2021-10-19

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Michel Jaouen ,  Stephane Le Roy ,  Moise Gergaud

IPC: G06F8/41 ,  G06F21/54 ,  G06F21/55

CPC classification number: G06F8/44 ,  G06F21/54 ,  G06F21/55 ,  G06F2221/033

Abstract: According to one aspect, a method for compiling by a compilation tool a source code into a computer-executable code comprises receiving the source code as input of the compilation tool, translating the source code into an object code comprising machine instructions executable by a processor, then introducing, between machine instructions of the object code, additional instructions selected from illegal instructions and no-operation instructions so as to obtain the executable code, then delivering the executable code as output of the compilation tool.

公开(公告)号：US20240039394A1

公开(公告)日：2024-02-01

申请号：US18486727

申请日：2023-10-13

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Lionel Cimaz

IPC: H02M1/32 ,  H02M3/02

CPC classification number: H02M1/32 ,  H02M3/02 ,  H02M1/0009

Abstract: In an embodiment a DC to DC conversion circuit includes a DC to DC converter connected to an input path and an output path and a current limiting circuit including a circuit configured to detect when an input or output current of the DC to DC converter exceeds or falls below a current threshold and a controller configured to store a first voltage level of an output voltage of the DC to DC converter in response to the input or output current exceeding the current threshold, to store a second voltage level of the output voltage in response to the input or output current falling below the current threshold and to set a control signal based on the first and second voltage levels.

公开(公告)号：US11886706B2

公开(公告)日：2024-01-30

申请号：US17558003

申请日：2021-12-21

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Frederic Darcel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/401

Abstract: A method includes receiving, by a device, of a control signal identifying a first application from among a plurality of compressed applications stored in a non-volatile memory of the device. The first application is stored in a first location of the non-volatile memory. The device decompresses the first application. The decompressing includes storing the decompressed first application into the non-volatile memory at least partially into the first location, and into a second location storing a second compressed application among the plurality of applications. The decompressed first application overwriting at least a portion of the second compressed application. The method may be performed as part of a customization process of an integrated circuit including the non-volatile memory.

公开(公告)号：US20240031301A1

公开(公告)日：2024-01-25

申请号：US18353784

申请日：2023-07-17

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Arnaud ROSAY ,  Florent CARLIER ,  Pascal LEROUX

IPC: H04L47/2483

CPC classification number: H04L47/2483

Abstract: A method of detecting network anomalies includes the reception, via an interface of an electronic device, of a first stream of packets sent by a source that is external and/or the transmission of a first stream of packets to a destination external; the computation, by a processing circuit, of a first packet stream identifier based on at least one of: a packet source address of the packets of the first stream; and a packet destination address of the first stream; searching, in an ordered dynamic data structure stored in a memory and including a plurality of entries. The searching is performed based on the value of the first packet stream identifier with respect to one or more search threshold values; and based on metadata associated with the first entry, blocking reception of the first stream of packets.