公开(公告)号：US20080003810A1

公开(公告)日：2008-01-03

申请号：US11823381

申请日：2007-06-27

Applicant: Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

Inventor： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC: H01L21/4763

CPC classification number: H01L27/1021

Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

Abstract translation: 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US20070063263A1

公开(公告)日：2007-03-22

申请号：US11602032

申请日：2006-11-20

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L29/788

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US20060186460A1

公开(公告)日：2006-08-24

申请号：US11301854

申请日：2005-12-13

Applicant: Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

Inventor： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC: H01L29/788 ,  H01L21/8238

CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract translation: 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US06563168B2

公开(公告)日：2003-05-13

申请号：US09989113

申请日：2001-11-21

Applicant: Yong-Kyu Lee

Inventor： Yong-Kyu Lee

IPC: H01L29788

CPC classification number: H01L27/11543 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/66825

Abstract: A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

Abstract translation: 一种非易失性半导体器件及其制造方法，该器件具有存储单元形成部分和具有高电压和低电压晶体管形成部分的外围电路部分，其中该器件包括围绕漏极区域的反穿通区域 存储单元形成部分以及低压晶体管形成部分的周围的漏极和源极区域。