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    Semiconductor device and method of fabricating semiconductor device
    2.
    发明授权
    Semiconductor device and method of fabricating semiconductor device 有权
    半导体器件及半导体器件的制造方法

    公开(公告)号：US08476130B2

    公开(公告)日：2013-07-02

    申请号：US13180613

    申请日：2011-07-12

    Applicant: Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

    Inventor： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

    IPC: H01L21/8238

    CPC classification number: H01L27/2436 ,  H01L27/105 ,  H01L27/2445 ,  H01L45/1683

    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

    Abstract translation: 一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

    Non-Volatile Memory Device
    3.
    发明申请
    Non-Volatile Memory Device 有权
    非易失性存储器件

    公开(公告)号：US20120087189A1

    公开(公告)日：2012-04-12

    申请号：US13177873

    申请日：2011-07-07

    Applicant: Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    IPC: G11C16/04

    CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

    Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

    Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device
    4.
    发明授权
    Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device 失效
    掩模ROM器件，包括掩模ROM器件的半导体器件，以及制造掩模ROM器件和半导体器件的方法

    公开(公告)号：US08053342B2

    公开(公告)日：2011-11-08

    申请号：US12836066

    申请日：2010-07-14

    Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

    Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

    IPC: H01L21/8238

    CPC classification number: H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

    Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

    Abstract translation: 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

    Non-volatile memory integrated circuit device and method of fabricating the same
    5.
    发明授权
    Non-volatile memory integrated circuit device and method of fabricating the same 失效
    非易失性存储器集成电路器件及其制造方法

    公开(公告)号：US07928492B2

    公开(公告)日：2011-04-19

    申请号：US11804329

    申请日：2007-05-17

    Applicant: Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    Inventor： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

    Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源区。

    Twin-ONO-type SONOS memory
    6.
    发明授权
    Twin-ONO-type SONOS memory 有权
    双ONO型SONOS存储器

    公开(公告)号：US07511334B2

    公开(公告)日：2009-03-31

    申请号：US11296397

    申请日：2005-12-08

    Applicant: Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

    Inventor： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

    IPC: H01L27/088 ,  H01L21/336

    CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

    Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

    Abstract translation: 双ONO型SONOS存储器包括具有源极区，漏极区和源极和漏极区之间的沟道区的半导体衬底，双氧化硅 - 氮化硅 - 氧化硅（ONO）电介质层，第一ONO电介质 在沟道区域和源极区域之间以及作为第二ONO电介质层位于沟道区域和漏极区域上的第一ONO介电层以及沟道区域上的控制栅极之间，在双ONO介电层之间，双ONO介电层沿着 邻近通道区域的控制栅极的最小下侧，其中双ONO电介质层朝着比控制栅极更远的源极和漏极区延伸。

    SPLIT GATE FLASH MEMORY DEVICE HAVING SELF-ALIGNED CONTROL GATE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SPLIT GATE FLASH MEMORY DEVICE HAVING SELF-ALIGNED CONTROL GATE AND METHOD OF MANUFACTURING THE SAME 有权
    具有自对准控制门的分离闸门闪存存储器件及其制造方法

    公开(公告)号：US20080111180A1

    公开(公告)日：2008-05-15

    申请号：US12014262

    申请日：2008-01-15

    Applicant: Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    Inventor： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    IPC: H01L29/788

    CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

    Abstract translation: 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

    FIN FIELD EFFECT TRANSISTORS INCLUDING OXIDATION BARRIER LAYERS
    9.
    发明申请
    FIN FIELD EFFECT TRANSISTORS INCLUDING OXIDATION BARRIER LAYERS 有权
    包括氧化阻挡层的FIN场效应晶体管

    公开(公告)号：US20080029828A1

    公开(公告)日：2008-02-07

    申请号：US11871453

    申请日：2007-10-12

    Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    IPC: H01L29/76 ,  H01L21/336

    CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

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