公开(公告)号：US06617639B1

公开(公告)日：2003-09-09

申请号：US10176594

申请日：2002-06-21

申请人： Zhigang Wang ,  Xin Guo ,  Yue-Song He

发明人： Zhigang Wang ,  Xin Guo ,  Yue-Song He

IPC分类号： H01L29788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883

摘要： A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.

摘要翻译： 一种浮栅闪存器件，包括：衬底，包括源极区，漏极区和位于其间的沟道区; 位于通道区域上方并通过隧道介电材料层与沟道区分离的浮栅电极; 以及控制栅电极，其位于所述浮置栅电极的上方，并且通过间隔电介质层与所述浮栅电极分离，所述互聚电介质层包括具有与所述浮栅电极相邻的底电介质材料层的修饰的ONO结构，顶介电材料 层，以及包括氮化物并位于底部电介质材料层和顶部电介质材料层之间的中心层，其中隧道电介质材料层和底部电介质材料层和底部电介质材料层中的至少一个 顶部介电材料层，包括高K电介质材料。

公开(公告)号：US06524914B1

公开(公告)日：2003-02-25

申请号：US09699972

申请日：2000-10-30

申请人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

发明人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

公开(公告)号：US06444539B1

公开(公告)日：2002-09-03

申请号：US09784892

申请日：2001-02-15

申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

IPC分类号： H01L2176

CPC分类号： H01L21/7621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

公开(公告)号：US06306707B1

公开(公告)日：2001-10-23

申请号：US09716659

申请日：2000-11-20

申请人： John Foster ,  Yue-Song He ,  Jiahua Huang

发明人： John Foster ,  Yue-Song He ,  Jiahua Huang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534

摘要： In the manufacture of an EPROM or EEPROM semiconductor device that includes a core region and a peripheral region, a nitride layer is formed over the core region and peripheral region, and an oxide layer is formed over the nitride layer. A layer of photoresist is provided over the oxide layer and is patterned to expose a portion of the oxide layer overlying the core region. A wet etch step is undertaken to remove the exposed portion of the oxide layer, using the patterned photoresist as a mask, and leaving exposed a portion of the nitride layer overlying the core region. After removal of the photoresist, the exposed portion of the nitride layer is etched by a wet etch step with hot phosphoric acid, using the pattered oxide layer as a mask.

摘要翻译： 在制造包括芯区域和周边区域的EPROM或EEPROM半导体器件中，在芯区域和外围区域上形成氮化物层，并且在氮化物层上形成氧化物层。 在氧化物层上提供一层光致抗蚀剂，并将其图案化以暴露覆盖芯区域的氧化物层的一部分。 进行湿蚀刻步骤以使用图案化的光致抗蚀剂作为掩模去除氧化物层的暴露部分，并且将覆盖在核心区域上的氮化物层的一部分暴露出来。 在去除光致抗蚀剂之后，使用图案化的氧化物层作为掩模，通过用热磷酸的湿蚀刻步骤蚀刻氮化物层的暴露部分。

公开(公告)号：US6153470A

公开(公告)日：2000-11-28

申请号：US374059

申请日：1999-08-12

申请人： Yue-Song He ,  Kent K. Chang ,  Jiahua Huang

发明人： Yue-Song He ,  Kent K. Chang ,  Jiahua Huang

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/72 ,  H01L31/072

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  Y10S438/923

摘要： A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.

摘要翻译： 一种形成浮动栅极以提高闪存器件的隧道氧化物可靠性的方法。 提供具有源极，漏极和沟道区域的衬底。 在衬底上形成隧道氧化物层。 在隧道氧化物和沟道区域上形成浮栅，浮栅是多层的，并且具有夹在第一层和第三层之间的第二层。 覆盖隧道氧化物层的浮置栅极的第一层包括未掺杂或轻掺杂的材料。 第二层是高度掺杂的。 第三层与电介质层直接接触，例如氧化物 - 氮化物 - 氧化物堆叠，并且由未掺杂或轻掺杂的材料制成。 介电材料形成在浮动栅极上，并且控制栅极形成在电介质材料上。