公开(公告)号：US20080046608A1

公开(公告)日：2008-02-21

申请号：US11925933

申请日：2007-10-27

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F3/00

CPC分类号： G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

摘要： An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an EUSB device that is busy performing a memory or other operation. Power is saved since polling is avoided. The busy EUSB device sends a not-yet NYET signal back to the EUSB host to instruct the host to enter the suspend mode. When the EUSB device is ready to continue transfer with the host, the EUSB device wakes up the host by sending a ready RDY signal back to the host. The NYET and RDY signals may be tokens or flags in serial packets sent over a full-duplex connection to the host with two sets of differential pairs. Transfers may be re-started by the host after suspension once the requested data is read from flash memory, or space is made available in a sector buffer by completing earlier writes to flash memory.

摘要翻译： 扩展的通用串行总线（EUSB）主机进入暂停模式，而不是轮询正忙于执行内存或其他操作的EUSB设备。 省电，因为避免轮询。 繁忙的EUSB设备向EUSB主机发送一个尚未发送的NYET信号，指示主机进入挂起模式。 当EUSB设备准备好继续与主机进行传输时，EUSB设备通过将准备好的RDY信号发送回主机来唤醒主机。 NYET和RDY信号可以是通过全双工连接发送到具有两组差分对的主机的串行数据包中的令牌或标志。 一旦所请求的数据从闪存中读取，主机可以重新启动传输，或者通过完成对闪存的更早写入，在扇区缓冲器中可用空间。

公开(公告)号：US20080003882A1

公开(公告)日：2008-01-03

申请号：US11846725

申请日：2007-08-29

申请人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

发明人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC分类号： H01R13/66

CPC分类号： G06K19/07743 ,  A45C2011/188 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/077 ,  G06K19/07732 ,  G07C9/00087 ,  H05K1/117 ,  H05K1/118 ,  H05K1/189 ,  H05K3/284 ,  H05K3/4691 ,  H05K2201/091 ,  H05K2201/10159 ,  H05K2203/1527

摘要： A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an external Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Dividers between openings in the upper case that expose the SD contact pads also support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB. A user-slidable switch may be slanted to compensate for the PCB slant. The PCB may have a flex section to facilitate the slant without a slanted switch.

摘要翻译： 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括一个外部安全数字（SD）接口，以及一个处理单元，用于从闪存芯片中读取数据块。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 暴露SD接触垫的上壳体中的开口之间的分隔线也以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜，以便为安装在PCB底部表面的芯片提供更大的厚度。 用户可滑动的开关可以倾斜以补偿PCB倾斜。 PCB可以具有弯曲部分以便于倾斜而没有倾斜的开关。

公开(公告)号：US20070274032A1

公开(公告)日：2007-11-29

申请号：US11309843

申请日：2006-10-11

申请人： Jim Ni ,  Abraham Ma ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jim Ni ,  Abraham Ma ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： H05K7/12 ,  H01L21/00

CPC分类号： H05K5/0269

摘要： A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.

摘要翻译： 闪存驱动器使用集成设备电子（IDE）接口替换硬盘驱动器。 闪存驱动器具有带有闪存芯片的电路板和控制器芯片的印刷电路板组件（PCBA）。 控制器芯片包括通过IDE接口连接到外部计算机的输入/输出接口电路，以及从闪速存储器芯片读取数据块的处理单元。 PCBA被封装在上壳体和下壳体内，并具有适合通过壳体和壳体之间打开的IDE连接器。 这些情况可以通过卡扣，超声波压力机，螺纹紧固件或热粘合粘合剂方法与PCBA组装。 形成在壳体内部的中心线适配在闪存芯片的行之间，以提高外壳刚度。 连接器具有跨越电路板中心线的两排销，用于平衡设计。

公开(公告)号：US20070130414A1

公开(公告)日：2007-06-07

申请号：US11309844

申请日：2006-10-11

申请人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

发明人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06K19/077 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/07732 ,  G07C9/00087 ,  Y02D10/13

摘要： A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.

摘要翻译： 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括通过安全数字（SD）接口连接到外部计算机的输入/输出接口电路，以及从闪速存储器芯片读取数据块的处理单元。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 在每个SD接触垫和中肋下的支撑端肋以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜，以允许安装在PCB底部表面的芯片的厚度更大，并且在插入端向下倾斜以将SD接触垫定位在中心线附近。

公开(公告)号：US20080082736A1

公开(公告)日：2008-04-03

申请号：US11864684

申请日：2007-09-28

申请人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7203 ,  G06F2212/7211

摘要： An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

摘要翻译： 由主机可访问的电子数据闪存卡包括连接到闪速存储器件的闪存控制器和被激活以建立与主机的通信的输入 - 输出接口电路。 在一个实施例中，闪存卡使用USB接口电路与主机进行通信。 闪速存储器控制器包括用于将逻辑地址与物理块地址对准的仲裁器，并且用于执行块管理操作，包括：将重新分配的数据存储到可用块，将过时块中的有效数据重定位到所述可用块并将逻辑块地址重新分配给物理块地址 的所述可用块，找到闪存设备的坏块并用备用块替换，在将有效数据重新定位到可用块之后擦除用于再循环的废弃块，以及擦除块的计数损耗均衡等。此外，每个闪存设备包括 内部缓冲区，用于加快块管理操作。

公开(公告)号：US20080003883A1

公开(公告)日：2008-01-03

申请号：US11846733

申请日：2007-08-29

申请人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

发明人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC分类号： H01R13/66

CPC分类号： G06K19/07743 ,  A45C2011/188 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/077 ,  G06K19/07732 ,  G07C9/00087 ,  H05K1/117 ,  H05K1/118 ,  H05K1/189 ,  H05K3/284 ,  H05K3/4691 ,  H05K2201/091 ,  H05K2201/10159 ,  H05K2203/1527

摘要： A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an external Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Dividers between openings in the upper case that expose the SD contact pads also support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. A metal switch-bar or an over-molded controller die may be substituted.

摘要翻译： 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括一个外部安全数字（SD）接口，以及一个处理单元，用于从闪存芯片中读取数据块。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 暴露SD接触垫的上壳体中的开口之间的分隔线也以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜以允许安装到PCB的底表面的芯片具有更大的厚度，并且在插入端向下倾斜以将SD接触垫定位在中心线附近。 金属开关杆或过模制的控制器管芯可以被替代。

公开(公告)号：US20080065788A1

公开(公告)日：2008-03-13

申请号：US11979102

申请日：2007-10-31

申请人： David Chow ,  Sidney Young ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Sidney Young ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/10

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G07C9/00087 ,  G07C2009/00095 ,  H01R13/629

摘要： A system for producing high volume flash memory cards includes a processing unit, a PC interface for connecting to an external PC, a PC drive circuit connected to the PC interface and the processing unit, a card interface for connecting to an external flash memory card, and a card drive circuit connected to the card interface and the processing unit. The PC drive circuit realizes communication between the PC and the processing unit. The card drive circuit realizes communication between the flash memory card and the processing unit. The processing unit receives command or data from the PC interface, and sends card re-initialization command or data to the flash memory card via the card interface.

摘要翻译： 一种用于生产大容量闪存卡的系统包括处理单元，用于连接到外部PC的PC接口，连接到PC接口的PC驱动电路和处理单元，用于连接到外部闪存卡的卡接口， 以及连接到卡接口和处理单元的卡驱动电路。 PC驱动电路实现PC与处理单元之间的通信。 卡驱动电路实现闪存卡和处理单元之间的通信。 处理单元从PC接口接收命令或数据，并通过卡接口将卡重新初始化命令或数据发送到闪存卡。

公开(公告)号：US20080034154A1

公开(公告)日：2008-02-07

申请号：US11871627

申请日：2007-10-12

申请人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

发明人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

公开(公告)号：US20080034153A1

公开(公告)日：2008-02-07

申请号：US11871011

申请日：2007-10-11

申请人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

发明人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C16/0408

摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。 闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

公开(公告)号：US20070180264A1

公开(公告)日：2007-08-02

申请号：US11693464

申请日：2007-03-29

申请人： Jim Ni ,  Ken Li ,  Abraham Ma ,  Ming-Shiang Shen

发明人： Jim Ni ,  Ken Li ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： H04L9/00 ,  H05K5/02 ,  G11C11/34 ,  H05K5/00

CPC分类号： H05K5/0269

摘要： A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through an opening between the cases. The cases can be assembled with the PCBA by a screw-together or thermal-bond adhesive method. Triple-axis case-grounding tabs draw any electro-static-discharges (ESD) current off the upper case along a primary axis and onto a PCBA ground through a secondary axis that is screwed into the PCBA. An intermediary axis between the primary and secondary axes fits around a PCBA notch while the secondary axis passes through a metalized alignment hole on the PCBA for grounding. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the triple-axis case-grounding tabs.

摘要翻译： 外壳接地闪存驱动器具有带闪存芯片的印刷电路板组件（PCBA）和控制器芯片。 PCBA被封装在上壳体和下壳体内，并具有通过壳体之间的开口配合的串行AT附件（SATA）连接器。 这些情况可以通过螺纹连接或热粘合粘合方法与PCBA组装。 三轴外壳接地卡舌通过主轴进入上壳体上的任何静电放电（ESD）电流，并通过螺纹连接到PCBA中的次轴上插入PCBA接地。 主轴和副轴之间的中间轴线位于PCBA切口周围，而副轴线穿过PCBA上的金属化对准孔接地。 当SATA连接器插入主机时，主机接地会吸收由三轴外壳接地片收集的ESD电流。