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117 条记录 (耗时 0.058 秒)

    Semiconductor device and method for fabricating the same
    81.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06713790B2

    公开(公告)日：2004-03-30

    申请号：US10212799

    申请日：2002-08-07

    申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    IPC分类号： H01L31072

    CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

    摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

    摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

    Method for driving a non-volatile semiconductor memory
    85.
    发明授权
    Method for driving a non-volatile semiconductor memory 失效
    用于驱动非易失性半导体存储器的方法

    公开(公告)号：US5715196A

    公开(公告)日：1998-02-03

    申请号：US684178

    申请日：1996-07-19

    申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

    摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

    Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same
    86.
    发明授权
    Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same 失效
    具有非易失性存储单元阵列的非易失性半导体存储器及其驱动方法

    公开(公告)号：US5627779A

    公开(公告)日：1997-05-06

    申请号：US505638

    申请日：1995-07-21

    申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/02

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

    摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

    Semiconductor device and method of manufacturing the same
    87.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5459341A

    公开(公告)日：1995-10-17

    申请号：US195165

    申请日：1994-02-14

    申请人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    发明人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed. With the second insulating layer of such configuration, an increase in connection resistance and a connection defect of the capacity storage electrode contact or the bit line contact are prevented.

    摘要翻译： P型半导体衬底的表面区域通过隔离形成半导体元件的多个有源区域来限定。 在每个有源区域上布置有诸如漏极区域的第一扩散区域，诸如源极区域的第二扩散区域和诸如字线的布线构件。 字线的表面被第一绝缘层覆盖。 提供了第二绝缘层，其中除去在至少两个第二扩散区域上共同的每个塔顶区域的区域，在第一扩散区域上留下顶部区域。 设置在第二扩散区域之上的是诸如容量存储电极，位线的导电构件。 连接导电部件和第二扩散区域的接触部件形成在除去第二绝缘层的区域。 通过这种结构的第二绝缘层，防止了电容存储电极接触或位线接触的连接电阻的增加和连接缺陷。

    Liquid injection recording system, a liquid injection head, a base plate for the recording head, and a recording apparatus having the liquid injection recording head
    89.
    发明授权
    Liquid injection recording system, a liquid injection head, a base plate for the recording head, and a recording apparatus having the liquid injection recording head 失效
    液体注射记录系统，液体注入头，用于记录头的底板，以及具有液体注射记录头的记录装置

    公开(公告)号：US4831391A

    公开(公告)日：1989-05-16

    申请号：US236290

    申请日：1988-08-25

    申请人： Akira Asai

    发明人： Akira Asai

    IPC分类号： B41J2/05 ,  B41J2/14 ,  B41J2/205

    CPC分类号： B41J2/14129 ,  B41J2002/14379 ,  B41J2202/03

    摘要： In a liquid injection recording system wherein an electrical signal is input to an electro-thermal conversion element to cause it to generate heat and produce bubbles in liquid and the liquid is injected by the action of the bubbles, a substance whose electrical resistance is varied by phase transition is used for a portion of the electro-thermal conversion element and harmonious recording is effected by the utilization of the phase transition characteristic of the substance.

    摘要翻译： 在液体注射记录系统中，其中电信号被输入到电热转换元件以使其产生热量并在液体中产生气泡，并且通过气泡的作用注入液体，将电阻改变为 相转变用于电热转换元件的一部分，并且通过利用物质的相变特性来实现和谐记录。

    Heat generating resistor, recording head using such resistor and drive method therefor
    90.
    发明授权
    Heat generating resistor, recording head using such resistor and drive method therefor 失效
    发热电阻，使用这种电阻的记录头及其驱动方法

    公开(公告)号：US4719478A

    公开(公告)日：1988-01-12

    申请号：US910727

    申请日：1986-09-23

    申请人： Masayoshi Tachihara ,  Shinichi Hirasawa ,  Masami Ikeda ,  Akira Asai ,  Hirokazu Komuro

    发明人： Masayoshi Tachihara ,  Shinichi Hirasawa ,  Masami Ikeda ,  Akira Asai ,  Hirokazu Komuro

    IPC分类号： B41J2/14 ,  G01D15/16

    CPC分类号： B41J2/14129 ,  B41J2/1412 ,  B41J2202/11

    摘要： A planar heat generating resistor has a heat generating resistor layer formed on or above a support member and a pair of opposing electrodes formed on the heat generating resistor layer, such that a width of the heat generating layer at the electrode area is larger than a width of the electrodes and a voltage is applied across the electrodes, in which a ratio of a maximum value of a gradient of .phi., .sqroot.(.differential..phi./.differential.x).sup.2 +(.differential..phi./.differential.y).sup.2 to a value of .sqroot.(.differential..phi./.differential.x).sup.2 +(.differential..phi./.differential.y).sup.2 at a center of the resistor is no larger than 1.4 when a Laplace equation .differential..sup.2 /.differential.x.sup.2 +.differential..sup.2 .phi./.differential.y.sup.2 =0 is solved for the heat generating resistor when an orthogonal coordinate system X-Y is defined on the resistor surface, a potential at a point (x,y) on the resistor surface is represented by .phi.(x,y), a boundary value is imparted to an area of a circumferential boundary of the resistor which contacts to one of the electrodes, a different boundary value is imparted to an area which contacts to the other electrode, and a boundary condition in which a differential coefficient of .phi. to a normal direction of the circumferential boundary is zero is imparted to an area which does not contact to any of the electrodes.

    摘要翻译： 平面发热电阻器具有形成在支撑构件上或上方的发热电阻层和形成在发热电阻层上的一对相对电极，使得电极区域处的发热层的宽度大于宽度 的电极上施加电压，其中phi，2ROOT（DIFFERENTIAL phi / DIFFERENTIAL x）2（DIFFERENTIAL phi / DIFFERENTIAL y）2的梯度的最大值与2ROOT值的比值 当求解拉普拉斯方程差分2 /差分x2 +差分2比特/差分y2 = 0时，电阻中心处的差分phi /差分x）2+（差分phi /差分y）2不大于1.4 电阻器，当电阻表面上定义正交坐标系XY时，电阻表面上的点（x，y）处的电位由phi（x，y）表示，边界值被赋予圆周边界的区域 与电极之一接触的电阻器，赋予与另一个电极接触的区域不同的边界值，并且赋予与周向边界的法线方向的微分系数为零的边界条件 到不与任何电极接触的区域。