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    Semiconductor device and method of manufacturing the same
    1.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5459341A

    公开(公告)日：1995-10-17

    申请号：US195165

    申请日：1994-02-14

    申请人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    发明人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed. With the second insulating layer of such configuration, an increase in connection resistance and a connection defect of the capacity storage electrode contact or the bit line contact are prevented.

    摘要翻译： P型半导体衬底的表面区域通过隔离形成半导体元件的多个有源区域来限定。 在每个有源区域上布置有诸如漏极区域的第一扩散区域，诸如源极区域的第二扩散区域和诸如字线的布线构件。 字线的表面被第一绝缘层覆盖。 提供了第二绝缘层，其中除去在至少两个第二扩散区域上共同的每个塔顶区域的区域，在第一扩散区域上留下顶部区域。 设置在第二扩散区域之上的是诸如容量存储电极，位线的导电构件。 连接导电部件和第二扩散区域的接触部件形成在除去第二绝缘层的区域。 通过这种结构的第二绝缘层，防止了电容存储电极接触或位线接触的连接电阻的增加和连接缺陷。

    Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
    2.
    发明授权
    Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window 失效
    一种用于制造包括接触窗的自对准形成的半导体集成电路器件的方法

    公开(公告)号：US5275972A

    公开(公告)日：1994-01-04

    申请号：US930485

    申请日：1992-08-14

    申请人： Hisashi Ogawa ,  Yasushi Naito ,  Masanori Fukumoto

    发明人： Hisashi Ogawa ,  Yasushi Naito ,  Masanori Fukumoto

    IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/283 ,  H01L21/31

    CPC分类号： H01L21/76897 ,  H01L21/76802 ,  Y10S438/97

    摘要： A fabrication method for a semiconductor integrated circuits which permits the self-aligned formation of contact windows without causing shorts or breaks in the interconnecting lines in the device is provided. After forming gate electrodes and source/drain regions of transistors on a semiconductor substrate, an etch-stop layer and a BPSG film are successively deposited over the gate electrodes and the source/drain regions. After a resist having a contact window pattern is formed on the BPSG film, an isotropic dry etching using a microwave plasma is performed to etch the BPSG film. According to the isotropic dry etching, the laterally etching rate in the BPSG film can be controlled by adjusting the RF power, and a silicon dioxide film can be used as the etch stop layer. After the BPSG flow process, the etch stop layer on the contact region is etched away to form contact windows.

    摘要翻译： 提供一种用于半导体集成电路的制造方法，其允许接触窗口的自对准形成而不引起装置中的互连线中的短路或断裂。 在半导体衬底上形成晶体管的栅电极和源极/漏极区之后，在栅电极和源极/漏极区上依次沉积蚀刻停止层和BPSG膜。 在BPSG膜上形成具有接触窗图案的抗蚀剂之后，使用微波等离子体进行各向同性的干蚀刻来蚀刻BPSG膜。 根据各向同性干蚀刻，可以通过调节RF功率来控制BPSG膜中的横向蚀刻速率，并且可以使用二氧化硅膜作为蚀刻停止层。 在BPSG流动过程之后，蚀刻掉接触区域上的蚀刻停止层以形成接触窗口。

    Semiconductor memory device and process
    5.
    发明授权
    Semiconductor memory device and process 失效
    半导体存储器件和工艺

    公开(公告)号：US5365095A

    公开(公告)日：1994-11-15

    申请号：US19577

    申请日：1993-02-18

    申请人： Tomofumi Shono ,  Teruhito Ohnishi ,  Masanori Fukumoto

    发明人： Tomofumi Shono ,  Teruhito Ohnishi ,  Masanori Fukumoto

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/532 ,  H01L27/105 ,  H01L27/108 ,  H01L27/02 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/53219 ,  H01L23/53223 ,  H01L23/53257 ,  H01L27/10808 ,  H01L2924/0002

    摘要： A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.

    摘要翻译： 提供了具有存储电容器的半导体存储器件，其具有大的存储容量以及高的组件密度，并且便于生产。 在半导体衬底中局部形成开关晶体管。 在晶体管上形成的是设置在其上的存储电容器的上层电线。 存储电容器触点通过上层导线。 在确保存储电容器接触的良好容量的同时，也可以在将上层电线的图案同时传送到存储单元区域以及外围电路区域上时，可以有利地获得焦点的允许。 特别地，通过使存储电容器的触点通过位线，漏极和源极可以与字线对称地布置，如具有位线存储 - 电容器组织单元的存储单元。 这消除了过多的部分，导致密度增加。

    Semiconductor memory device having a trench-stacked capacitor
    6.
    发明授权
    Semiconductor memory device having a trench-stacked capacitor 失效
    具有沟槽叠层电容器的半导体存储器件

    公开(公告)号：US5047815A

    公开(公告)日：1991-09-10

    申请号：US394123

    申请日：1989-08-14

    申请人： Mitsuo Yasuhira ,  Takatoshi Yasui ,  Kazuhiro Matsuyama ,  Hideyuki Iwata ,  Masanori Fukumoto

    发明人： Mitsuo Yasuhira ,  Takatoshi Yasui ,  Kazuhiro Matsuyama ,  Hideyuki Iwata ,  Masanori Fukumoto

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.

    摘要翻译： 半导体存储器件包括在开关晶体管周围形成的沟槽中的电容器和绝缘分离区域，电容器的存储电极夹在上和下单元电极板电极之间，以减少由寄生MOS晶体管效应引起的漏电流 在开关晶体管中的通道的沟槽侧壁中，由于在沟槽侧壁中的栅极控制的二极管效应引起的漏电流。 此外，公开了一种用于制造这种半导体存储器件的方法。

    Method for manufacturing a semiconductor memory device
    7.
    发明授权
    Method for manufacturing a semiconductor memory device 失效
    半导体存储器件的制造方法

    公开(公告)号：US5242852A

    公开(公告)日：1993-09-07

    申请号：US944883

    申请日：1992-09-11

    申请人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

    发明人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

    CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L28/40 ,  Y10S438/908

    摘要： In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.

    摘要翻译： 在以堆叠式存储单元型制造DRAM的方法中，蚀刻第一绝缘膜时，每个位线的边缘部分被露出，裸露的边缘部分被从开口蚀刻并且开口的内周面被 第二绝缘膜。 还公开了一种方法，其中第二绝缘膜和第三绝缘膜和第二导电膜堆叠在第一绝缘膜上，形成第二导电膜，并且第二导电膜和第一导电膜被部分蚀刻，由此第一绝缘膜的未蚀刻部分 导电膜用作电荷存储电极的电极平面。

    Method of manufacturing a semiconductor device
    8.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5677220A

    公开(公告)日：1997-10-14

    申请号：US478110

    申请日：1995-06-07

    申请人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    发明人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed. With the second insulating layer of such configuration, an increase in connection resistance and a connection defect of the capacity storage electrode contact or the bit line contact are prevented.

    摘要翻译： P型半导体衬底的表面区域通过隔离形成半导体元件的多个有源区域来限定。 在每个有源区域上布置有诸如漏极区域的第一扩散区域，诸如源极区域的第二扩散区域和诸如字线的布线构件。 字线的表面被第一绝缘层覆盖。 提供了第二绝缘层，其中除去在至少两个第二扩散区域上共同的每个塔顶区域的区域，在第一扩散区域上留下顶部区域。 设置在第二扩散区域之上的是诸如容量存储电极，位线的导电构件。 连接导电部件和第二扩散区域的接触部件形成在除去第二绝缘层的区域。 通过这种结构的第二绝缘层，防止了电容存储电极接触或位线接触的连接电阻的增加和连接缺陷。

    Semiconductor device and process
    9.
    发明授权
    Semiconductor device and process 失效
    半导体器件和工艺

    公开(公告)号：US5633211A

    公开(公告)日：1997-05-27

    申请号：US347114

    申请日：1994-11-23

    申请人： Shinichi Imai ,  Yuka Terai ,  Masanori Fukumoto ,  Kousaku Yano ,  Hiroyuki Umimoto ,  Shinji Odanaka ,  Yasuo Mizuno

    发明人： Shinichi Imai ,  Yuka Terai ,  Masanori Fukumoto ,  Kousaku Yano ,  Hiroyuki Umimoto ,  Shinji Odanaka ,  Yasuo Mizuno

    IPC分类号： C23C16/40 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/02

    CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/0215 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/31625 ,  H01L21/31629

    摘要： The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.

    摘要翻译： 由于半导体器件的电介质膜的平坦化在较低的流动温度下进行，因此令人满意地保持半导体器件的特性。 在作为电介质膜的二氧化硅膜的情况下，网状结构由作为主要成分的硅原子和作为电介质膜的基体的副成分的氧原子构成。 这些氧原子被诸如卤素原子包括氟的非桥连组分替代。 在发生这种替换的位置上，这通过氧原子在硅原子之间断开桥。 因此，电介质膜的粘度随流动温度而下降。 例如，如果BPSG膜中的氧的一部分被氟取代，则允许电介质膜在850℃的较低温度下流动。可以抑制短的通道效应。