公开(公告)号：US07989882B2

公开(公告)日：2011-08-02

申请号：US11952447

申请日：2007-12-07

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US07856529B2

公开(公告)日：2010-12-21

申请号：US11786581

申请日：2007-04-12

申请人： Shripad Nagarkar ,  Rodric Rabbah ,  Anant Agarwal

发明人： Shripad Nagarkar ,  Rodric Rabbah ,  Anant Agarwal

IPC分类号： G06F12/08

CPC分类号： G06F12/0864

摘要： Methods and apparatus related to memory indexing. Receiving indications of an indexing function for use with a memory. Performing indexing functions with a processor before addressing a memory location. Referencing a customizable lookup table to determine a memory location. Translating a computer program to control a computer system to use a desired indexing function. Determining desired indexing functions based on performance of a computer system.

摘要翻译： 与记忆索引相关的方法和设备。 接收与存储器一起使用的索引功能的指示。 在寻址内存位置之前，使用处理器执行索引功能。 引用可定制的查找表来确定内存位置。 翻译计算机程序以控制计算机系统使用所需的索引功能。 根据计算机系统的性能确定所需的索引功能。

公开(公告)号：US07805577B1

公开(公告)日：2010-09-28

申请号：US11404655

申请日：2006-04-14

申请人： Matthew Mattina ,  David Wentzlaff ,  Anant Agarwal

发明人： Matthew Mattina ,  David Wentzlaff ,  Anant Agarwal

IPC分类号： G06F12/06

CPC分类号： G06F12/0817 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/1036 ,  Y02D10/13

摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。 集成电路还包括一个或多个存储器接口模块，其包括用于访问外部存储器的电路，每个存储器接口模块耦合到至少一个瓦片的开关。 至少一些瓦片被配置为向存储器接口模块发送消息以确定与瓦片相关联的先前存储器事务是否已经完成。

公开(公告)号：US07805575B1

公开(公告)日：2010-09-28

申请号：US11754118

申请日：2007-05-25

申请人： Anant Agarwal ,  Ian R. Bratt ,  Matthew Mattina

发明人： Anant Agarwal ,  Ian R. Bratt ,  Matthew Mattina

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817

摘要： A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.

摘要翻译： 多核处理器包括多个高速缓冲存储器; 多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联; 以及多个存储器接口，其提供从高速缓存存储器到主存储器的存储器访问路径，至少一些存储器接口提供到多个高速缓存存储器的主存储器的访问路径。 每个存储器接口与主存储器的相应部分相关联，并且包括用于主存储器的该部分的目录控制器。

公开(公告)号：US07805392B1

公开(公告)日：2010-09-28

申请号：US11564694

申请日：2006-11-29

申请人： Kenneth M. Steele ,  Anant Agarwal

发明人： Kenneth M. Steele ,  Anant Agarwal

IPC分类号： G06N5/02

CPC分类号： G06F17/30982 ,  G06F21/564 ,  H04L69/16 ,  H04L69/161 ,  H04L69/22

摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.

摘要翻译： 多个互连处理引擎中的模式匹配包括：通过接口接收输入序列流并存储输入序列; 存储用于将输入序列与用于由第一组一个或多个处理引擎访问的存储器中的一个或多个模式进行匹配的指令，以及存储用于将输入序列匹配到存储器中的一个或多个模式的指令，所述指令可由第二组一个或多个 处理发动机; 将识别所选输入序列的信息分发到所述第一和第二组处理引擎; 以及检索所识别的输入序列以在所述第一和第二组处理引擎中执行模式匹配。

公开(公告)号：US07774579B1

公开(公告)日：2010-08-10

申请号：US11404461

申请日：2006-04-14

申请人： David Wentzlaff ,  Anant Agarwal

发明人： David Wentzlaff ,  Anant Agarwal

IPC分类号： G06F15/163

CPC分类号： G06F15/8007

摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The tile is configured to control access to a resource of the tile based on access information associated with the resource.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。 该瓦片被配置为基于与资源相关联的访问信息来控制对瓦片的资源的访问。

公开(公告)号：US07673164B1

公开(公告)日：2010-03-02

申请号：US11300649

申请日：2005-12-13

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： G06F1/32

CPC分类号： G06F15/8007 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851 ,  G06F15/17381 ,  G06F15/7867 ,  H03K19/177 ,  H03K19/17704 ,  Y02D10/12 ,  Y02D10/13

摘要： An integrated circuit includes a plurality of tiles. Each tile includes a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; and a timer. At least some tiles include a low power mode of operation in which either the processor or the switch is able to be powered down, and the tile is able to leave the low power mode based at least in part on a value of the timer.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器; 开关，其包括切换电路，用于通过数据路径将数据从其他瓦片转发到处理器以及其他瓦片的切换; 和一个计时器。 至少一些瓦片包括低功率操作模式，其中处理器或开关能够断电，并且瓦片能够至少部分地基于定时器的值而离开低功率模式。

公开(公告)号：US07577820B1

公开(公告)日：2009-08-18

申请号：US11404958

申请日：2006-04-14

申请人： David Wentzlaff ,  Anant Agarwal

发明人： David Wentzlaff ,  Anant Agarwal

IPC分类号： G06F15/76

CPC分类号： G06F15/16

摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片 从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

公开(公告)号：US07394288B1

公开(公告)日：2008-07-01

申请号：US11302984

申请日：2005-12-13

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： G06F15/8007 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851 ,  G06F15/17381 ,  G06F15/7867 ,  H03K19/177 ,  H03K19/17704 ,  Y02D10/12 ,  Y02D10/13

摘要： An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器，开关，其包括用于将数据从其他瓦片转发到处理器的数据路径以及其他瓦片的切换的切换电路;以及存储指令流的开关存储器，所述指令流能够独立地对于相应输出端口 开关。

公开(公告)号：US06804814B1

公开(公告)日：2004-10-12

申请号：US09474680

申请日：1999-12-29

申请人： Andrew E. Ayers ,  Richard Schooler ,  Anant Agarwal

发明人： Andrew E. Ayers ,  Richard Schooler ,  Anant Agarwal

IPC分类号： G06F944

CPC分类号： G06F11/3636 ,  G06F11/3624 ,  G06F11/3644

摘要： A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace. In one embodiment, the instruction trace is displayed and a value set is determined for an instruction upon a request by the user indicating the instruction for which the value set is desired.

摘要翻译： 程序执行数据跟踪是通过在程序执行过程中记录数值集和指令跟踪进行测量而创建的。 通过根据指令轨迹从与从设定到第二指令的记录值相关联的第一指令向后或向前模拟指令，为第二指令确定值集合。 后向和前向模拟可以相互补充。 为了进行反向仿真，优选地保持模拟指令表，其将在指令轨迹中遇到的程序指令与反转相关程序指令的操作的模拟指令相关联。 优选地，将一个或多个探针插入到程序中以保存其值可能难以确定的特定变量的值。 优选地，指示轨迹显示在数据轨迹旁边并与之相关联。 在一个实施例中，显示指令轨迹，并且在用户请求时指示针对期望值设置的指令的指令确定值集合。