利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.027 秒)

    Mapping memory in a parallel processing environment
    3.
    发明授权
    Mapping memory in a parallel processing environment 有权
    在并行处理环境中映射内存

    公开(公告)号：US07620791B1

    公开(公告)日：2009-11-17

    申请号：US11404207

    申请日：2006-04-14

    申请人： David Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

    发明人： David Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

    IPC分类号： G06F12/08

    CPC分类号： G06F12/1027 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0844

    摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further includes a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory.

    摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。 集成电路还包括多个存储器接口模块，其包括用于访问相应的外部存储器的电路，每个存储器接口模块耦合到至少一个瓦片的开关。 至少一些瓦片被配置为通过从交换机发送包括包括外部存储器地址的物理存储器地址和识别对应的外部存储器的信息的分组来访问外部存储器中的地址。

    Managing set associative cache memory according to entry type
    4.
    发明授权
    Managing set associative cache memory according to entry type 有权
    根据条目类型管理集合关联高速缓存

    公开(公告)号：US07461210B1

    公开(公告)日：2008-12-02

    申请号：US11404654

    申请日：2006-04-14

    申请人： David Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

    发明人： David Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

    IPC分类号： G06F12/06

    CPC分类号： G06F12/126 ,  G06F12/0864 ,  G06F2212/1021

    摘要： Managing memory includes: mediating access to a first memory as a cache for a second memory; and associating one of a plurality of entry types with entries in the cache. Data from the second memory associated with a first type is not allowed to evict a cache entry associated with a second type.

    摘要翻译： 管理存储器包括：将作为第二存储器的缓存的第一存储器的访问中介; 以及将多个条目类型中的一个与所述高速缓存中的条目相关联。 来自与第一类型相关联的第二存储器的数据不允许驱逐与第二类型相关联的高速缓存条目。

    Managing memory access in a parallel processing environment
    5.
    发明授权
    Managing memory access in a parallel processing environment 有权
    在并行处理环境中管理内存访问

    公开(公告)号：US07805577B1

    公开(公告)日：2010-09-28

    申请号：US11404655

    申请日：2006-04-14

    申请人： Matthew Mattina ,  David Wentzlaff ,  Anant Agarwal

    发明人： Matthew Mattina ,  David Wentzlaff ,  Anant Agarwal

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0817 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/1036 ,  Y02D10/13

    摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.

    摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。 集成电路还包括一个或多个存储器接口模块，其包括用于访问外部存储器的电路，每个存储器接口模块耦合到至少一个瓦片的开关。 至少一些瓦片被配置为向存储器接口模块发送消息以确定与瓦片相关联的先前存储器事务是否已经完成。

    Managing data provided to switches in a parallel processing environment
    7.
    发明授权
    Managing data provided to switches in a parallel processing environment 有权
    在并行处理环境中管理提供给交换机的数据

    公开(公告)号：US08127111B1

    公开(公告)日：2012-02-28

    申请号：US12110956

    申请日：2008-04-28

    申请人： David Wentzlaff ,  Anant Agarwal

    发明人： David Wentzlaff ,  Anant Agarwal

    IPC分类号： G06F15/00

    CPC分类号： G06F15/16

    摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.

    摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片 从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

    Coupling data for interrupt processing in a parallel processing environment
    8.
    发明授权
    Coupling data for interrupt processing in a parallel processing environment 有权
    在并行处理环境中耦合中断处理数据

    公开(公告)号：US08190855B1

    公开(公告)日：2012-05-29

    申请号：US12036918

    申请日：2008-02-25

    申请人： Carl G. Ramey ,  David Wentzlaff ,  Anant Agarwal

    发明人： Carl G. Ramey ,  David Wentzlaff ,  Anant Agarwal

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/30003 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3853 ,  G06F15/17381 ,  G06F15/8023 ,  H04L49/101 ,  H04L49/109 ,  H04L49/251

    摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.

    摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。 集成电路还包括一个或多个接口模块，其包括用于将数据传送到和从外部的设备传输到数据块的电路; 以及子端口路由网络，其包括用于在交换机的端口与耦合到一个或多个接口模块的多个子端口之间路由数据的电路。