公开(公告)号：US08211770B2

公开(公告)日：2012-07-03

申请号：US13167806

申请日：2011-06-24

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US20110250737A1

公开(公告)日：2011-10-13

申请号：US13167806

申请日：2011-06-24

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US09064710B2

公开(公告)日：2015-06-23

申请号：US13482311

申请日：2012-05-29

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流以形成AMOSFET，其在导通状态下的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US20090146154A1

公开(公告)日：2009-06-11

申请号：US11952447

申请日：2007-12-07

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/24 ,  H01L29/78 ,  H01L29/74 ,  H01L21/04

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US20120235164A1

公开(公告)日：2012-09-20

申请号：US13482311

申请日：2012-05-29

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/16 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US07989882B2

公开(公告)日：2011-08-02

申请号：US11952447

申请日：2007-12-07

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US20120280252A1

公开(公告)日：2012-11-08

申请号：US13102510

申请日：2011-05-06

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/12 ,  H01L29/06 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

公开(公告)号：US09142662B2

公开(公告)日：2015-09-22

申请号：US13108440

申请日：2011-05-16

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定 在井区域中的通道区域。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。

公开(公告)号：US09029945B2

公开(公告)日：2015-05-12

申请号：US13102510

申请日：2011-05-06

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区，以及阱区中的源极区。 源区具有第一导电类型并且在阱区中限定沟道区。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。

公开(公告)号：US20120280270A1

公开(公告)日：2012-11-08

申请号：US13108440

申请日：2011-05-16

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定 在井区域中的通道区域。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。